Roland A. - PVD for microelectronics (779636), страница 26
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Tanaka et al. [5.21] have found that the yield of cleanedsubmicron vias was a strong function of Ar § energy, which they attributedto the lower gas scattering and increased directionality of higher-energy Arions. It seems likely that some chemical component will need to be addedto sputter cleaning in the future to deal with very high aspect ratio features(e.g., the use of Ar/H 2 or other reactive gas mixtures) or that a more traditional RIE or even a vapor-phase clean will be used.Under conditions of high-rate sputter etching (e.g., 500 &/min removalof SiO 2 with 500 eV Ar § the incident power density can be > 0.5 W/cm 2,which can heat the wafer well above 100~ The temperature reached bythe wafer during preclean is important for several reasons. First of all, ifthe wafer gets too hot during sputter cleaning, sufficient water vapor canbe released from the exposed SOG sidewalls to poison contacts and viasduring PVD deposition.
This same effect must be considered when precleaning, as pointed out by Wolters and Heesters [5.22]. For example, consider the 1.0-/xm-diameter via shown in Fig. 5.21, which is patterned in asandwich of 0 . 2 / z m of SOG over 0.8/xm of CVD oxide. In this case, thegoal of the sputter preclean is to remove A1203 from AI at the bottom of thevia. Water vapor that is evolved from the via sidewalls is assumed to comefrom the exposed "ring" of SOG, whose surface area is ~ 10 -8 cm 2.Studies have shown that the desorption rate of H20 from SOG is -~ 5 x10 -6 Torr-1/sec-cm 2 ( ~ 2 x 1014 H20 molecules/sec-cm 2) for glass temperatures in the range of ~ 100-400~Therefore, at elevated temperatures, ~ 2 x 1014 x 10 -8 -- 2 x 106 H20 molecules/sec are released.Given the area of the via bottom (8 x 10 -9 c m 2) and a typical sputter etchremoval rate of AI203 (50 ,~/min = 2 x 1013 A1203 molecules/sec-cm2), itis easy to see that the amount of water vapor entering the via from its side-SPUTTERING TOOLSFIG.
5.21cleaning.133Illustration of how outgassing of SOG can reoxidize the bottom of a via during sputterwall could be 10 times greater than the amount of material being removedfrom the via bottom (2 x 105 AI203 molecules/sec). This can lead to thealuminum being oxidized at a faster rate than it is removed, which underscores the need for a proper degas.A related oxygen-contamination issue is the fact that the blanket natureof sputter etching means that the field oxide (SiO2) over the entire wafersurface is also being removed, sputter ejecting O from a surface area thatvastly exceeds that of the exposed vias to be cleaned of AI203. Under conditions of high-rate via etching, SiO 2 etch rates can be 600 )~/min, and onecan calculate that undesirably high O partial pressures ( > 7 x 1 0 - 4 Yorr)can result unless effective pumping speed for O is very high (>> 40 1/sec).Therefore, vacuum pumps used on a preclean module should have relatively high pumping speed for both oxygen and water vapor.Another concern with elevated temperature during preclean of contactsrelates to device damage m primarily wafer charging that damages thingate oxides.
More specifically, charging induces Fowler-Nordheim tunneling of electrons through thin oxides that generate traps, resulting in degraded electrical properties such as leakage. Device damage during reactive plasma or inert sputter etching is a complex topic, dependent on such134R. POWELL AND S. M. ROSSNAGELthings as oxide thickness, plasma uniformity, and device structure [5.23,5.24].
One measure of an oxide's susceptibility to charging damage is itscharge-to-breakdown (Qbd)' with damage starting to appear when the electron fluence (electron current x time) passing through the oxide exceeds acritical threshold value ~ typically ~ 1% of Qbd"Since Qbddecreases withtemperature, lower-temperature precleaning allows thin oxides to be exposed to a greater total charge before the onset of damage. In addition totraps generated by electrons tunneling through the oxide toward the Sibelow, holes injected from the Si into the oxide can also generate traps.Since the mobility of the holes is temperature dependent, higher temperatures lead to more damage.
As a practical matter, keeping wafer temperature less than ~ 100~ during contact preclean is probably acceptable for0.25-/xm device fabrication, although more advanced ULSI devices mayrequire preclean temperatures of room temperature or below. Concernsabout temperature are relaxed for via cleaning, and some users employ relatively high temperatures ( ~ 400~during via preclean because the additional wafer outgassing (the wafer has already been vacuum-annealed inthe degas module) is found to improve the reliability of a step such as reflow A1, which is influenced by even trace amounts of water.Figure 5.22 lists representative process attributes of an advanced precleaning module. Throughput requirements for the overall PVD process require etch rates sufficiently high to remove native oxides of Si and A1 atthe bottom of high aspect ratio features in times < 60 sec.
On the otherhand, customer concerns about ion-induced damage have required the useof lower Ar + ion energy for both contact- and via-level cleaning (e.g.,<< 100 eV for contacts). Because the sputter yield is reduced by going tolower energy, these two requirements have led suppliers to develop higherdensity plasma sources with high ion flux at low energy. It is instructive toestimate the required ion flux density to remove 100 A of SiO 2 in 1 minuteor less. At relatively low ion energy (<< 1 keV), the sputter yield Y isfound to have a square-root dependence on ion energy E of the form Y =A ( E I/2 - E~)/2), where both the sputtering threshold E 0 and the constant Adepend on the ion-substrate combination.
For Ar + on SiO 2, E 0 ~ 30 eV andA ~ 3.5 x 10 -2 molecules/ion-eV 1/2, giving a sputter yield at 100 eV ofY ~ 0.15 molecules/ion. Since the atomic density of silicon oxide is 2.3 x1022 molecules/cm 3, sputter etching away 100 A of SiO 2 in 1 minute or lesswill then require an incident Ar + flux of > 2.5 x I0 ~5 ions/cmZ-sec.Advanced plasma sources can provide such ion flux densities, and thepower density at 100 eV is small enough ( ~ 40 mW/cm 2) that appreciatewafer heating does not occur during the short preclean time.SPUTTERING TOOLSFIG.
5.22135Process attributes desired for an advanced precleaning module for PVD.Concerns about contamination and directionality (from gas-phase scattering) are also driving preclean process pressure below 1 mTorr, while theneed to reduce particles is promoting a move away from mechanical edgeclamps or rings (which can be sputter deposited onto the wafer) and towardelectrostatic chucks (e-chucks) or clampless processes. A further advantage of an electrostatic chuck is that it allows one to retain the use of backside-gas-assisted heat transfer between the wafer and chuck, facilitatingcontrol of temperature during the process. Even using an e-chuck, however, material sputtered from the wafer surface can redeposit onto the wallsof the precleaning chamber.
Although 200 ~ or less of oxide is typicallyremoved per wafer, after a large number of wafers are precleaned (e.g.,1000), a rather thick film deposit can build up on the shields (e.g., 20/zm),which itself becomes a source of contamination and/or particles. A numberof methods have been developed to increase the amount of deposit that theinterior shielding can bear before they have to be replaced and/or cleaned.For example, shield surfaces can be perforated, which allows the contaminants to pass through and coat the outside of the shields and other interior parts of the chamber.
This effectively increases the surface area ofthe shields and the time between shield cleaning. Another approach is to136R. POWELL AND S. M. ROSSNAGELtexture the shield surfaces by bead or sand blasting or by sputter etching inan effort to increase the adhesion of the deposit. Suitably treated, theshields can then retain a greater mass of deposited material before flakingor exfoliating particles.Figure 5.23 shows several hardware configurations that have been usedfor preclean: diode and magnetically enhanced diode, and two highdensity, low-pressure plasma approaches u electron cyclotron resonance(ECR) and inductively coupled plasma (ICP).
Both the ECR and ICP areshown with an independent RF bias applied to the wafer. The flexibilityprovided by a dual-frequency etch permits incident ion energy and ion fluxSeveral hardware configurations have been used for precleaning of wafer prior to PVD,including diode, magnetically enhanced diode, electron cyclotron resonance (ECR), and inductivelycoupled plasma (ICP).FIG.
5.23SPUTTERING TOOLS137to be varied more or less independently. Also note that there are many similarities between hardware for dual-frequency ICP preclean and hardwarebeing developed for directional, RF-ionized PVD (see Chapter 8 ) ~ although the application (sputter preclean vs directional deposition) and theprocess pressure ( < 1 mTorr vs ~ 20-50 mTorr), among other things, arequite different.5 . 3 .
4 WAFER TEMPERATUREEven though wafers enter and exit a PVD cluster tool at near room temperature ( ~ 20~their thermal history in passing through the tool can beextremely complicated, exhibiting a temperature vs time profile that is dependent on the specific process and hardware used. In general, wafer temperature varies from ~ 20~ to 450~ in a cluster tool during PVD processing, in contrast to front-end-of-line processes such as thermaloxidation or ion implantation activation annealing, which can involve temperatures as high as 900-1000~ As we have seen, during degas the waferis brought rapidly up to a high temperature ( ~ 450~and held for nearly60 sec for water vapor outgassing of thick interlayer oxides. However, during a similar 60 sec of sputter precleaning, it is desirable to limit wafertemperature rise to below ~ 100~ to minimize damage to thin gate oxides.
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