Roland A. - PVD for microelectronics (779636), страница 31
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Therefore, a realistic holding pressure of the chuck might be 10times lower than given by Eq. (5.8), but in any case is more than sufficientto hold a wafer in place against backside gas pressures of ~ 5 Torr. Also,since thin films of alumina and related ceramics can be deposited withgood quality (e.g., low leakage current at elevated temperature), relativelylow applied voltages can be used (e.g., 500 V for a 200-/zm thick insulator) to provide suitable holding force for PVD applications.An important potential benefit of an ESC is that backside gas can beused without frontside holding.
However, to prevent wafer bowing thewafer should be pulled down uniformly over its entire area (e.g., not justelectrostatically clamped at the edge) and the distribution of gas should besuch that it provides uniform heat transfer. Figure 5.36 shows several designs of open gas channels, or grooves, that have been created at the dielectric surface for this purpose. In general, a combination of concentricWafer on Grooved ESCF-......'IBackside GasFIG. 5.36 Illustration of grooving in the surface of an ESC to obtain good surface contact and distribution of backside gas over the wafer area. Gas enters at the large dots and is distributed through anetwork of radial and linear troughs.160R. POWELL AND S.
M. ROSSNAGELrings and radial lines are used. Making the grooves too numerous and/ortoo deep can reduce the attractive force by increasing h gap in Eq. (5.7).Also, heat transfer efficiency within the groove is reduced if the gap dimension exceeds the mean free path of gas (see Section 5.3.4). Finally,placing grooves too close to the wafer edge to improve temperature uniformity can lead to gas leakage into the process volume. Grooves also reduce the area of physical contact between chuck and wafer, which reducesthe potential for tribologically generated particles.Well-designed ESCs are capable of holding 5 Torr or more of BSA withAr leakage < 0.1 or 0.2 sccm, which is much less than the ~ 50 sccm ofAr typically used during PVD. On the other hand, leakage of even ppmlevels of contamination into the chamber is to be avoided, and this suggests that ultrahigh-purity Ar gas should be used for the chuck.
Also, theleak rate around the chuck may rule out the use of gases such as He forbackside gas heat transfer since a sustained leak rate of even 0.1 sccm ofHe may be sufficient to dump the cyropump on the process chamber.The simple chuck in Fig. 5.35 is a monopolar design; more common forPVD is a bipolar design (Fig. 5.37) in which different portions of the waferare clamped by oppositely charged electrodes. While the bipolar design ismore complicated, one advantage is that for equal electrode areas withequal and opposite voltage drops to the wafer, no net charge need flow tothe wafer. The wafer can then be held at any time in the process step or inmoving parts such as a robotic handler.In addition to the usual considerations of using an ESC in vacuum processing (cost, reliability, and particles), there are three materials-related issues that are especially relevant to PVD: (1) high vacuum compatibility,(2) high-temperature operation, and (3) dechucking.High Vacuum and High Temperature Electrostatic chucks were first introduced into microelectronics in the early 1970s for holding wafers flatduring photolithography [5.38] and have become common on advancedplasma etching systems for wafer cooling.
Their application to PVD hasbeen more difficult because the materials of construction must be compatible with both UHV base pressure (e.g., low outgassing rate) and high temperature ( ~ 500~This rules out both polymeric coatings as well as anumber of high-k ceramics that are compatible with high vacuum but aretoo leaky at high temperature. The most common ESC dielectric candidatefor PVD is alumina (A1203)m either single crystal (i.e., sapphire) or as aplasma-sprayed or anodized film m with other ceramics of interest including aluminosilicates, A1N, B N, and diamond.SPUTTERING TOOLSFIG. 5.37161Bipolar ESC design.De-chucking De-chucking refers to the controlled removal of the attractive force.
When the applied voltage is turned off, a wafer can still stickto the chuck due to residual forces m e.g., from permanent bulk polarization of the dielectric (many ceramics of interest for an ESC are highly polarizable) or from charge trapped at the dielectric surface or back of awafer with an insulating oxide or nitride film. If the time required for thischarge to leak off is large (>> 1 sec), wafer throughput will be reduced. Inthis regard, one approach that has been used successfully for ion implantapplications is the six-electrode "hexapolar" design shown in Fig.
5.38.Application of a square wave of opposite polarity to each of the three pairsof dielectric sectors creates three bipolar chucks. By choosing the voltage162R. POWELL AND S. M. ROSSNAGELFIG. 5.38 Six-electrode ESC that combines the high holding force of a DC e-chuck with the rapidrelease time of an AC e-chuck [5.37].to each bipolar chuck to be 120 ~ out of phase, when the voltage goesthrough zero for any one bipolar chuck, the other two are at full holdingforce.
This allows a large holding force to be produced as with a DC chuck,but because the applied voltage is AC, no significant DC polarization occurs. This design has permitted dechucking in < 80 msec.SPUTTERING TOOLS163While having a wafer stuck to the chuck after deposition is clearly undesirable, a related concern is the possibility of not having a wafer presenton the e-chuck during deposition.
That is, if the PVD tool fails to sense thata wafer is not on the e-chuck and begins metal deposition, the surface insulation of the chuck will be shorted out and the chuck will have to be removed and cleaned or replaced - - a costly proposition. For example, in thechuck shown in Fig. 5.38, the transient current flowing in the wafer whenthe chuck is first energized is used to sense whether the wafer is on or offthe chuck, since the magnitude of this current depends strongly on the capacitance between wafer and chuck.5 .
3 . 6 PARTICLES AND OTHER FOREIGN MATTERGiven the critical influence of device yield on functional cost (e.g., the costper bit of memory on a DRAM), improvements in overall defect densitywill be needed to allow cost-effective production of ever-smaller deviceson ever-larger die (see Fig. 5.39).
Because the minimum feature size of thetypical IC has decreased so rapidly over time, particles of a size consideredharmless in past device generations are now potential "killer" defects. Forexample, 0.25-/zm device roadmaps call for contamination-free manufacturing at the level of below ~ 0.016 defects/cm 2 = 160 defects/m 2 for bothDRAMs and microprocessors [5.39], where a defect is any structural flaw,contamination, particle, etc. that causes a chip to fail electrically.
ThisAllowable particulate contamination for each generation of DRAM and microprocessorICs (after ref. 5.39).FIG. 5.39164R. POWELL AND S. M. ROSSNAGELlevel corresponds to < 5 such defects over a 200-mm wafer. Defects associated with fine submicron size particles (--< 0.12/xm) are a critical yieldreducing agent in ULSI devices, and increasingly these are introducedwithin the process tool itself [5.40].Particles added onto the wafer surface as a result of either robotictransport (mechanical adders) or processing (process adders) within aPVD cluster tool can have a significant effect on device yield, which inturn leads to a higher cost-of-ownership.
A representative PVD particlespecification for 0.25-/xm device production is < 125 particles/m 2 of size-> 0.08/xm. For a 200-mm wafer without edge exclusion (314 cm2), thisallows only about 4 such particles to be added per wafer. While the particle density allowed for next-generation 0.18-/xm technology is expectedto be similar to that at 0.25/.,m, the size limit on the added particles willbe reduced from 0.08 /xm to 0.06 /xm. In this regard, there is concernwhether metrology will be available to map and quantify such low particle levels on metal films, which is a challenge for conventional laser lightscattering methods.
We next briefly discuss common sources of particlesand related foreign matter (FM) encountered in PVD cluster tool processing as well as practices that tool suppliers and users have used to reduce their levels.Clean RoomWhen an open wafer cassette is moved between process tools within an ultrahigh-quality clean room, the level of exposure to particulate contamination is very low (e.g., a Class 1 clean room has less than about 35 particles/ft 3 of size 0.1 /xm and greater). On the other hand, a non-negligibleconcentration of volatile hydrocarbons can exist in clean-room air, whichcan lead to surface adsorption during wafer transport or storage. The resuiting hydrocarbon film may be quite t h i n - only a monolayer or sobut can give rise to reliability issues during subsequent PVD processing.For example, if the wafer undergoes a rapid heating step, the hydrocarbonfilm may not have time to thermally desorb, but instead may crack or reactwith exposed Si to form SiC.
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