Roland A. - PVD for microelectronics (779636), страница 34
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Also, when the IC industry174R. POWELL AND S. M. ROSSNAGELswitched to 200 mm, PVD equipment capable of 8-inch processing waspurchased and used initially for 6-inch product wafers. The cost premiumof a 300-mm tool (by some estimates 70% or more) will probably not giverise to a similar retrofit equipment market. More likely, 300-mm tools willinitially be used for production-proven 200-mm processes (e.g., 0.25 p m )before adding the extra risk of next-generation device technology (e.g.,0.18 pm).
This also allows for the problem of "missing" 300-mm technologies that are needed to establish a complete IC fab line but may not beavailable early on in the conversion from 200 mm to 300 mm. Using a 300mm PVD tool for 200-mm production relaxes this problem but adds considerable cost per wafer due to the increased 300-mm tool cost.5.5 PVD Process MappingIn Chapters 9 and 1 1 a number of materials and process issues associatedwith PVD contacts, barriers, and interconnects used in MLM will be discussed. Regardless of their specific metallurgy, all these materials are deposited using vacuum-integrated multistep recipes that can be brokendown for analysis into separable "process blocks" (e.g., degas, preclean,PVD deposition, anneal), separated in time from one another by a combination of robotic wafer handling, vacuum valving, and pumping steps.Mapping a PVD process sequence in this graphical way allows one to assess the impact o f non-value-added time (e.g., time associated with wafer handling or valve sequencing) and identify ways to improve waferthroughput.
To illustrate process mapping, we consider a representativePVD Al process for simultaneous via fill and interconnect planarization ofan advanced 0.25-pm geometry device (Fig. 5.44). A two-step process(TSP) consisting of sequential cold Al and hot Al deposition in a singlePVD module is used for this purpose.
The detailed steps and timing of thisprocess are dependent on the specific cluster tool used. Therefore, the information shown on the process map in Fig. 5.44 is intended for illustration only and should not be taken literally as a process recipe.Figure 5.44a shows the basic sequence in which an incoming wafer isdegassed, precleaned by a sputter etch, and then sequentially depositedwith a collimated PVD Ti wetting layer, via-filled using a cold-hot PVD Aldeposition in the same chamber, and then coated with a TiN ARC layer(see Chapter 7). Fig. 5.44b maps the wafer's progress through the steps ofdegas and preclean etch preceding PVD Ti deposition. As can be seen, thetime spent on actual processing (degas = 50 sec; preclean = 30 sec) iscomparable to the total overhead time associated with wafer motion,175SPUTTERINGTOOLSl'=r~' f-[ "co,."~ .voA,~.vo.,.,,.=, r I ,..c,(~~PVD Ti- [ ~ PVD A'DegasClole laolatlonV~ve~Waferon Ta~LoedWl~ron Arm1 secfrom Table10 sec1 sec)~"'~1 secRetract Arm1 secI~ u"'-''~1"1"-A"1 sec1 sec"==1 sec0.5 sec1 sec1 secc,~=.,.~iIsolationValve1 sec.......3 secIkl s~and Purge50 secAnn Extend=Rotate Arm1 sec1 sec1~c'---'~'="~1 sec0.5 sec1 sec1 secPrec,ean30 secC1 sec~ t~=*-o.,..1 sec0.5 secIo...o,.,o~10 sec1 sec(b)Map for a representative PVD AI planarization integrated process sequence, with detailsshown from degas through preclean.FIG.
5.44176R. POWELLAND S. M. ROSSNAGELvacuum valving and pumping, and wafer thermal management (e.g., a 10sec cooldown after preclean etching). While not mapped out in detail inFig. 5.44, the remainder of the planarized cold-hot AI process (PVD Ti +PVD A1 cold + PVD A1 hot + PVD TiN) would consume about 270 sec ofprocess time but only about 80 sec of handling time. In this part of theprocess sequence, the overhead time is much less than the time associatedwith actual PVD deposition m primarily because the two-step A1 processtime is relatively long ( ~ 150-200 sec).
An analysis of this kind might leadto the use of two modules to carry out parallel PVD cold-hot A1, which appears to be the rate-limiting process step on overall tool throughput.5.6 Cost-of-Ownership (COO)It has been predicted that the single largest increase in IC manufacturingcosts through the year 2000 will come from capital equipment (Fig. 5.45),and this in turn has focused considerable attention on cost-of-ownershipmodeling and reduction [5.49-5.51]. When PVD was introduced intomicroelectronic manufacturing in the 1970s, equipment selection wasweighted heavily ( ~ 60%) by process performance m e.g., the improvedFIG. 5.45 The single largest increase in IC manufacturing cost from 1991 through 2000 is estimatedto come from capital equipment (Source: W.
Rhines, Texas Instruments).SPUqqqERING TOOLS177step coverage of PVD over e-beam evaporation or the fact that one PVDsystem had vacuum loadlocks for improved A1 film quality. However, bythe 1990s, tool selection was based on more or less equal considerationsof cost-of-ownership, equipment price, support, and performance (seeFig. 5.46). For commodity products like DRAMs that are produced witha low profit margin (e.g., 20%), even a slight increase in return on investment of capital assets ( + 1%) can have a significant impact on grossmargins ( + 5%). Therefore, increasing tool productivity has become a keyelement in the strategic business plans for both equipment suppliers andusers.The strategic importance of tool productivity can be quantified by considering the cost per function of a chip, which has historically been reduced over time by 25-30% per year (Fig.
5.47). For example, in 1975 thecost per bit of memory in a 4K DRAM was ~ 0.2 cents, while in 1995 thecost per bit of a 64M DRAM was ~ 2 x 10 -5 cents. This exponential decrease reflects the IC industry's strategy of shrinking device dimensions onFIG. 5.46 Relative importance of cost-of-ownership in equipment purchase decisions has increasedsignificantly over the last 20 years (after Fig. 2 in ref.
5.52) (Source: W. Rhines, Texas Instruments).R. POWELL AND S. M. ROSSNAGEL178Fealure Size-- 12%-14%Ar0Im0C-3%--12%-14%Waler Size,,., , , = = , . ~ ,Yield ImprovementO.""O}0"~ ~,,,,. ~ , , """""'--<2.%--~<1%Other Produclivily--Equipment, elc.00,.J"Equicment Pro(fuctMty|25% - 30%/Yr.>9%-15%ImprovementTime1995FIG. 5.47 Through about 1995, a combination of feature size reduction, water size increase, yieldimprovement, and "other" productivity enhancements enabled a 25-30% annual reduction in cost perfunction. To continue on this historical curve well into the future, equipment productivity must improve to compensate for diminishing returns in other areas (Source: B.
Owens, SEMATECH).average every 3 years and increasing wafer size every 7 years or so. As aresult, the cost of a chip has increased much more slowly than the totalcomputing power or memory it provides, and cost per function has decreased dramatically. Figure 5.47 also breaks out the four factors that haveaccounted for the 25-30% annual improvement in cost per function: feature size reduction, wafer size increase, yield improvement, and "other"enhancements [5.43]. SEMATECH has analyzed the further gains expectedfrom going to ULSI devices and 300-mm wafers, leading to the extrapolated curve in Fig.
5.46. Since the first three factors are predicted to flatten out, the IC industry can only keep on its historical cost productivitycurve through dramatic improvements (9-15% per year) in the "other" categorya category dominated by process tool productivity.Cost-of-ownership is a quantifiable measure of the actual investmentrepresented by a process tool. Being a high-level parameter, CoO is dependent on a large number of subfactors related to equipment design andoperation. Hence, using spreadsheet analysis, the sensitivity of CoO tochanges in tool configuration or use can be assessed. Not surprisingly,major contributions to CoO generally turn out to be tool selling price,throughput of functional die and tool reliability (e.g., mean-(productive)SPUTTERING TOOLS179time-between-failures = MTBFp), availability (e.g., uptime), and maintainability (e.g., mean-time-to-repair = MTTR).
Given the importance ofthe latter three attributes and the potential confusion over how to quantifythem, an industry standard m SEMI Standard E l 0 m for "Definition andMeasurement of Equipment Reliability, Availability, and Maintainability"was created in 1996 [5.54]. For example, MTBFp is defined as productivetime divided by the number of failures that occur during this time.
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