Roland A. - PVD for microelectronics (779636), страница 36
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Vac. Sci. & Tech. B13(4): 1910-1916 (1995).5.36. J.-E Daviet, L. Peccoud, and E Mondon, "Electrostatic clamping applied to semiconductorplasma processing," J. Electrochem. Soc. 140(I 1): 3245-3261 (1993).5.37. B. Frutiger, R. Eddy, D. Brown and M. Mack, "Production proven electrostatic platen forSPUTTERING TOOLS5.38.5.39.5.40.5.41.5.42.5.43.5.44.5.45.5.46.5.47.5.48.5.49.5.50.5.51.5.52.5.53.5.54.5.55.183medium current implantation," Proc. l l t h Int. Conf.
on Ion Implant Techn. - - H T ' 9 6 , abstractT20 (Austin, TX, June 16-21, 1996).G. A. Wardly, "Electrostatic wafer chuck for electron beam microfabrication," Rev. Sci. Instr.44(10): 1506-1509 (1973).The National Technology Roadmap f o r Semiconductors, p. 126, Semiconductor IndustryAssociation, San Jose, CA 1994.J.A. Cunningham, "The remarkable trend in defect densities and chip yields," Semicond. Int.,86-90 (June 1992).B. Y.-H. Liu, "How particles form during vacuum pump down," Semicond. Int., 75-80 (Mar.1994).G. S.
Selwyn, C. A. Weiss, E Sequeda, and C. Huang, "Particle contamination formation inmagnetron sputtering processes," J. Vac. Soc. & Tech. A15(4): 2023-2028 (1997).E. Korczynski, "Design challenges in vacuum robotics," Solid State Tech., 62-70 (Oct. 1996).Proc. First Forum on 300 mm Equipment Design, SEMATECH, Santa Clara, CA, May 12,1995.K.-M. Kim, "Growing improved silicon crystals for VLSI/ULSI applications," Solid StateTech., 70-80 (Nov. 1996).W. Fosnight, R. Martin, and A.
Bonora, "300 mm - - A new frontier," Solid State Tech., 77-81(Feb. 1996).M. A. Drew, M. G. Hanssmann, and D. Camporese, "Automation and control for 300-mmprocess tools," Solid State 7~,ch., 51-64 (Jan. 1997).C. Van Leeuwen, "Implications of 300 mm for tab design and automation," Semicond. Int.,91-96 (Apr. 1996).J. Secrest and P. Burggraaf, "The reasoning behind 'cost of ownership'," Semicond. Int., 56-60(May 1993).R.
L. LaFrance and S. B. Westratc, "Cost of ownership: The supplicr's view," Solid State Tech.,33-37 (July 1993).P. Singer, "!996: A ncw tocus on equipment effectiveness," Semicond. Int., 70-74 (Jan. 1996).W. Rhines, Texas Instruments (Fig. 1 in ref. 5.49).J. Owens, SEMATECH (Fig. 1 in ref. 5.51).V. H. Dhudshia, "SEMI E l 0 - - E q u i p m e n t reliability, availability and maintainability,"Semicond. Int., 167-174 (June 1997).P. Singer, "The driving lbrces in cluster tool development," Semicond. Int., 113-118 (July1995).This Page Intentionally Left BlankChapter 6 Directional DepositionThe sputter emission process was described in Chapter 2 in terms of a cosine-like angular distribution for the sputtered atoms.
Although variationsin this distribution are routinely observed, the general trend is that sputtered atoms are ejected from the target surface in a broad range of angles.Practical sputter deposition tools, described in Chapter 5, are usually characterized by short target-to-sample (throw) distances of a few centimetersand relatively large target diameters or lateral dimensions, often 50%larger than the (wafer) sample to be deposited on.These two features m the broad angular emission distribution and theshort throw distance m plus any in-flight gas scattering that might deflectthe sputtered atoms even more, result in a depositing flux to the samplesurface that is nearly isotropic.
This differs significantly from the case oflow-pressure evaporation where all the atoms arrive at normal incidence.The isotropic sputtered flux results in good coverage and film continuityover bumps and steps on the film surface (Fig. 6.1); this was originally oneof the great advantages of sputter deposition for microelectronic applications. The term step coverage was originally defined to describe this ability to continuously cover vertical steps on the surface. The sputtered filmsalso contributed to the planarization of the surface. This effect could be enhanced by the imposition of a sample bias (usually RF) during deposition,which would cause resputtering of the growing film. This resulted due tothe enhanced sputter yield at moderate angles in a smoother, more planarsurface that could be more easily patterned lithographically.The deposition of interconnect features on semiconductor wafers relieson this smooth, nearly planar metal layer deposited by sputtering.Photoresist layers are then deposited on the metal layer, patterned by optical exposure, and developed onto a contact-surface mask layer that willprotect and delineate the underlying metal circuit pattern.
The unwantedmetal between the photoresist-protected lines is then etched away using atechnique known as reactive ion etching (RIE), in which chemically activeions, such as F1- or CI-, bombard the surface and form volatile metal fluorides or chlorides, which are then pumped away in the vacuum system.Once the unwanted metal is completely etched away, the resist layer canbe chemically stripped. This leaves behind the underlying, protected metalcircuit lines on the surface.
Subsequent layers of oxide (deposited from aliquid, from a chemical vapor process, or even by sputtering) are depositedonto the metal lines providing the base for the next metallization level.There are two, reasonably fundamental problems with this RIE metallization technology. The first is due to the intrinsic nonplanarity of the185R. POWELL AND S. M. ROSSNAGEL186Deposited FilmSubstrateFIG. 6.ISchematic of sputter deposition over a step.deposition.
Even though the metal layers are reasonably smooth, etchingthem into lines and pads results in a topographically varied surface (i.e.,lines and spaces between the lines). The subsequent dielectric depositionis moderately smooth but can result in various undulations and bumps asthe oxide covers over the metal lines. This surface undulation makes subsequent photoresist patterning more difficult due to depth-of-focus problems, and the undulations become more severe as the number of layersincreases.
This limits RIE metallization interconnect schemes to typically 3 to 4 layers.The second, more practical problem is that whereas RIE of Al is characterized by a reasonably high vapor pressure for the product molecules at atypical processing temperature of 200°C, the same cannot be said for RIEof Cu. The vapor pressure for the Cu-chlorides is about 2 orders of magnitude lower than for the A1 products.
For the case of etching AICu, this canleave behind an enriched Cu layer unless additional ion bombardment isused during the RIE. This may not be desirable due to redeposition and/orbeveling problems intrinsic to resputtering. This problem with Cu also precludes the eventual transition over to a Cu-based interconnect metallization, which is desirable for its lower resistance and subsequently lower RCpropagation delays.DIRECTIONAL DEPOSITION1876.1 Damascene ProcessingIn the early 1990s an alternate lithography process for ULSI applicationswas developed at IBM m damascene processing [6.1].
This process isshown in several steps in Fig. 6.2. The first step is the deposition of a planar dielectric film, typically either silicon dioxide (or a related glassystructure) or a polymer such as polyimide. Next, features are lithographically patterned into the dielectric by means of photoresist deposition, exposure, and processing and then reactive ion etching (RIE) through the resist mask. The features produced are typically holes, known as vias, ortrenches that function as interconnect conduction lines. Once the trenchesor vias are etched, the mask is removed.The next step (Fig.
6.2c) is the deposition of metal into the feature suchthat it is completely filled to the top of the original dielectric surface. Itmay be appropriate to use several levels of metal in this feature, perhapswith thin layers for adhesion, interdiffusion resistance, or seeding. Thefinal step (Fig 6.2d) is to remove the overdeposit of metal from the "field"FIG. 6.2 Damascene process: (a) oxide deposition and resist exposure, (b) RIE through mask toform via, (c) metal deposition, (d) CMP removal of overdeposit.188R. POWELLAND S. M.
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