Микроконтроллер Motorola 68HC11 (1086181), страница 23
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In normal modes, PR[1:0]can only be written once, and the write must be within 64 cycles after reset. Refer toTable 9-1 and Table 9-4 for specific timing values.Table 9-4 Timer Prescale9PR[1:0]Prescaler0010141081116NOTEBits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones inTMSK2 enable the corresponding interrupt sources.9.3.10 Timer Interrupt Flag Register 2Bits in this register indicate when certain timer system events have occurred. Coupledwith the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem tooperate in either a polled or interrupt driven system. Each bit of TFLG2 correspondsto a bit in TMSK2 in the same position.TFLG2 — Timer Interrupt Flag 2RESET:Bit 7TOF06RTIF0$10255PAOVF04PAIF03—02—01—0Bit 0—0Clear flags by writing a one to the corresponding bit position(s).TOF — Timer Overflow Interrupt FlagSet when TCNT changes from $FFFF to $0000RTIF — Real Time (Periodic) Interrupt FlagRefer to 9.4 Real-Time Interrupt.PAOVF — Pulse Accumulator Overflow Interrupt FlagRefer to 9.6 Pulse Accumulator.PAIF — Pulse Accumulator Input Edge Interrupt FlagRefer to 9.6 Pulse Accumulator.MOTOROLA9-12TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATABits [3:0] — Not implementedAlways read zero9.4 Real-Time InterruptThe real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixedperiodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulseaccumulator control (PACTL) register.
The RTII bit in the TMSK2 register enables theinterrupt capability. The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR[1:0]. Refer to Table 9-5, which shows theperiodic real-time interrupt rates.Table 9-5 RTI RatesRTR[1:0]E = 3 MHzE = 2 MHzE = 1 MHzE = X MHz000110112.731 ms5.461 ms10.923 ms21.845 ms4.096 ms8.192 ms16.384 ms32.768 ms8.192 ms16.384 ms32.768 ms65.536 ms(E/213)(E/214)(E/215)(E/216)The clock source for the RTI function is a free-running clock that cannot be stopped orinterrupted except by reset.
This clock causes the time between successive RTI timeouts to be a constant that is independent of the software latencies associated with flagclearing and service. For this reason, an RTI period starts from the previous timeout,not from when RTIF is cleared.Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interruptrequest is generated. After reset, one entire RTI period elapses before the RTIF flagis set for the first time. Refer to the TMSK2, TFLG2, and PACTL registers.9.4.1 Timer Interrupt Mask Register 2This register contains the real-time interrupt enable bits.TMSK2 — Timer Interrupt Mask Register 2RESET:Bit 7TOI06RTII05PAOVI04PAII0$10243—02—01PR10Bit 0PR00TOI — Timer Overflow Interrupt Enable0 = TOF interrupts disabled1 = Interrupt requested when TOF is set to oneRTII — Real-Time Interrupt Enable0 = RTIF interrupts disabled1 = Interrupt requested when RTIF set to onePAOVI — Pulse Accumulator Overflow Interrupt EnableRefer to 9.6 Pulse Accumulator.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-139PAII — Pulse Accumulator Input EdgeRefer to 9.6 Pulse Accumulator.Bits [3:2] — Not implementedAlways read zeroPR[1:0] — Timer Prescaler SelectRefer to Table 9-4.NOTEBits in TMSK2 correspond bit for bit with flag bits in TFLG2.
Ones inTMSK2 enable the corresponding interrupt sources.99.4.2 Timer Interrupt Flag Register 2Bits of this register indicate the occurrence of timer system events. Coupled with thefour high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operatein either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit inTMSK2 in the same position.TFLG2 — Timer Interrupt Flag 2RESET:Bit 7TOF06RTIF0$10255PAOVF04PAIF03—02—01—0Bit 0—0Clear flags by writing a one to the corresponding bit position(s).TOF — Timer Overflow Interrupt FlagSet when TCNT changes from $FFFF to $0000RTIF — Real-Time Interrupt FlagThe RTIF status bit is automatically set to one at the end of every RTI period. To clearRTIF, write a byte to TFLG2 with bit 6 set.PAOVF — Pulse Accumulator Overflow Interrupt FlagRefer to 9.6 Pulse Accumulator.PAIF — Pulse Accumulator Input Edge Interrupt FlagRefer to 9.6 Pulse Accumulator.Bits [3:0] — Not implementedAlways read zero9.4.3 Pulse Accumulator Control RegisterBits RTR[1:0] of this register select the rate for the RTI system.
The remaining bits control the pulse accumulator and IC4/OC5 functions.MOTOROLA9-14TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATAPACTL — Pulse Accumulator ControlRESET:Bit 7DDRA706PAEN05PAMOD0$10264PEDGE03DDRA302I4/O501RTR10Bit 0RTR00DDRA7 — Data Direction for Port A Bit 7Refer to SECTION 6 PARALLEL INPUT/OUTPUT.PAEN — Pulse Accumulator System EnableRefer to 9.6 Pulse Accumulator.PAMOD — Pulse Accumulator ModeRefer to 9.6 Pulse Accumulator.PEDGE — Pulse Accumulator Edge ControlRefer to 9.6 Pulse Accumulator.9DDRA3 — Data Direction for Port A Bit 3Refer to SECTION 6 PARALLEL INPUT/OUTPUT.I4/O5 — Input Capture 4/Output CompareRefer to 9.6 Pulse Accumulator.RTR[1:0] — RTI Interrupt Rate SelectThese two bits determine the rate at which the RTI system requests interrupts.
TheRTI system is driven by an E divided by 213 rate clock that is compensated so it is independent of the timer prescaler. These two control bits select an additional divisionfactor. Refer to Table 9-5.9.5 Computer Operating Properly Watchdog FunctionThe clocking chain for the COP function, tapped off of the main timer divider chain, isonly superficially related to the main timer system.
The CR[1:0] bits in the OPTIONregister and the NOCOP bit in the CONFIG register determine the status of the COPfunction. One additional register, COPRST, is used to arm and clear the COP watchdog reset system. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed discussion of the COP function.9.6 Pulse AccumulatorThe M68HC11 family of MCUs have an 8-bit counter that can be configured to operateeither as a simple event counter or for gated time accumulation, depending on thestate of the PAMOD bit in the PACTL register.
Refer to the pulse accumulator blockdiagram, Figure 9-3. In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. The maximum clocking rate for the external eventcounting mode is the E clock divided by two. In gated time accumulation mode, a freerunning E-clock ÷64 signal drives the 8-bit counter, but only while the external PAI pinis activated. Refer to Table 9-6.
The pulse accumulator counter can be read or writtenat any time.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-15PAOVIPAOVF1INTERRUPTREQUESTSPAIIPAIF2PAOVFPAIFPAOVIPAIIE ÷ 64 CLOCK(FROM MAIN TIMER)TMSK2 INT ENABLESTFLG2 INTERRUPT STATUSPAI EDGEPAENDISABLEFLAG SETTINGOVERFLOWMCU PINPA7/PAI/OC1CLOCKENABLEDATABUSOUTPUTBUFFERFROMMAIN TIMEROC1FROMDDRA7PACNT 8-BIT COUNTERPAENPAENPAMODPEDGE92:1MUXINPUT BUFFERANDEDGE DETECTORPACTL CONTROLINTERNALDATA BUSPULSE ACC BLOCKFigure 9-3 Pulse AccumulatorTable 9-6 Pulse Accumulator TimingCrystalFrequencyE ClockCycle TimeE ÷ 64PACNTOverflow4.0 MHz1 MHz1000 ns64 µs16.384 ms8.0 MHz2 MHz500 ns32 µs8.192 ms12.0 MHz3 MHz333 ns21.33 µs5.461 msPulse accumulator control bits are also located within two timer registers, TMSK2 andTFLG2, as described in the following paragraphs.9.6.1 Pulse Accumulator Control RegisterFour of this register’s bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two other bits select the ratefor the real-time interrupt system.MOTOROLA9-16TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATAPACTL — Pulse Accumulator ControlRESET:Bit 7DDRA706PAEN05PAMOD0$10264PEDGE03DDRA302I4/O501RTR10Bit 0RTR00DDRA7 — Data Direction for Port A Bit 7Refer to SECTION 6 PARALLEL INPUT/OUTPUT.PAEN — Pulse Accumulator System Enable0 = Pulse accumulator disabled1 = Pulse accumulator enabledPAMOD — Pulse Accumulator Mode0 = Event counter1 = Gated time accumulationPEDGE — Pulse Accumulator Edge ControlThis bit has different meanings depending on the state of the PAMOD bit, as shown inTable 9-7.Table 9-7 Pulse Accumulator Edge ControlPAMODPEDGEAction on Clock00PAI falling edge increments the counter.01PAI rising edge increments the counter.10A zero on PAI inhibits counting.11A one on PAI inhibits counting.DDRA3 — Data Direction for Port A Bit 3Refer to SECTION 6 PARALLEL INPUT/OUTPUT.I4/O5 — Input Capture 4/Output Compare 50 = Output compare 5 function enable (No IC4)1 = Input capture 4 function enable (No OC5)RTR[1:0] — RTI Interrupt Rate SelectsRefer to 9.4 Real-Time Interrupt.9.6.2 Pulse Accumulator Count RegisterThis 8-bit read/write register contains the count of external input events at the PAI input, or the accumulated count.
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