Микроконтроллер Motorola 68HC11 (1086181), страница 27
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Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage.2. Performance verified down to 2.5 V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5 V ±10%.MOTOROLAA-16ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-6a Analog-To-Digital Converter Characteristics (MC68L11E9)VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, 750 kHz ≤E ≤2.0 MHz, unless otherwise notedCharacteristicParameterMinAbsoluteMaxUnitResolutionNumber of Bits Resolved by A/D Converter—8—BitsNon-LinearityMaximum Deviation from the Ideal A/D TransferCharacteristics——±1LSBZero ErrorDifference Between the Output of an Ideal and anActual for Zero Input Voltage——±1LSBFull Scale ErrorDifference Between the Output of an Ideal and anActual A/D for Full-Scale Input Voltage——±1LSBTotal UnadjustedErrorMaximum Sum of Non-Linearity, Zero Error, andFull-Scale Error——±1 1/2LSBQuantization ErrorUncertainty Because of Converter Resolution——±1/2LSBAbsolute AccuracyDifference Between the Actual Input Voltage andthe Full-Scale Weighted Equivalent of theBinary Output Code, All Error SourcesIncluded——±2LSBConversion RangeAnalog Input Voltage RangeVRL—VRHVVRHMaximum Analog Reference VoltageVRL—VDD + 0.1VVRLMinimum Analog Reference VoltageVSS –0.1—VRHV∆VRMinimum Difference between VRH and VRL3.0——VConversion TimeTotal Time to Perform a SingleAnalog-to-Digital Conversion:E Clock—32—tcycInternal RC Oscillator——tcyc + 32µsConversion Result Never Decreases with anIncrease in Input Voltage and has no MissingCodes—Guaranteed——Zero Input Reading Conversion Result when Vin = VRL00——HexFull Scale ReadingConversion Result when Vin = VRH——FFHexSampleAnalog Input Acquisition Sampling Time:E Clock—12—tcycInternal RC Oscillator——12µsMonotonicityAcquisition TimeSample/HoldCapacitanceInput Capacitance During SamplePE[7:0]—20 (Typ)—pFInput LeakageInput Leakage on A/D PinsPE[7:0]——400nAVRL, VRH——1.0µANOTES:1.
Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-17ATable A-7 Expansion Bus TimingVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to THNumCharacteristicSymbolFrequency of Operation (E-Clock Frequency)1Cycle Time2Pulse Width, E LowPWEL = 1/2 tcyc –23 ns(Note 1)Pulse Width, E HighPWEH = 1/2 tcyc –28 ns(Note 1)34a4bE and AS Rise TimeE and AS Fall Time9Address Hold TimetAH = 1/8 tcyc –29.5 ns12A(Note 1, 2a)Nonmultiplexed Address Valid Time to E RisetAV = PWEL –(tASD + 80 ns) (Note 1, 2a)1.0 MHzMinMax2.0 MHzMinMax3.0 MHzMinMaxUnitfodc1.0dc2.0dc3.0MHztcyc1000—500—333—nsPWEL477—227—146—nsPWEH472—222—141—nstrtf——2020——2020——2015nstAH95.5—33—26—nstAV281.5—94—54—ns17Read Data Setup TimetDSR30—30—30—ns18Read Data Hold Time (Max = tMAD)tDHR0145.5083051ns19Write Data Delay TimetDDW = 1/8 tcyc + 65.5 nstDDW—190.5—12871ns(Note 1, 2a)Write Data Hold TimetDHW = 1/8 tcyc –29.5 nstDHW95.5—33—26—ns(Note 1, 2a)2122Multiplexed Address Valid Time to E RisetAVM = PWEL –(tASD + 90 ns) (Note 1, 2a)tAVM271.5—84—54—ns24Multiplexed Address Valid Time to AS Fall(Note 1)tASL = PWASH –70 nstASL151—26—13—ns25Multiplexed Address Hold TimetAHL = 1/8 tcyc –29.5 nstAHL95.5—33—31—ns(Note 1, 2b)Delay Time, E to AS RisetASD = 1/8 tcyc –9.5 nstASD115.5—53—31—ns(Note 1, 2a)PWASH221—96—63—nstASED115.5—53—31—ns196—ns111ns—ns262728Pulse Width, AS HighPWASH = 1/4 tcyc –29 nsDelay Time, AS to E RisetASED = 1/8 tcyc –9.5 ns(Note 1)(Note 1, 2b)29MPU Address Access Time(Note 2a)tACCA = tcyc –(PWEL–tAVM) –tDSR–tftACCA744.5—307—35MPU Access TimetACCE = PWEH –tDSRtACCE—442—19236Multiplexed Address Delay(Previous Cycle MPU Read)(Note 1, 2a)tMAD = tASD + 30 nstMAD145.5—83—511.
Formula only for dc to 2 MHz.2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clockduty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the followingexpressions in place of 1/8 tcyc in the above formulas, where applicable:(a) (1–DC) × 1/4 tcyc(b) DC × 1/4 tcycWhere:DC is the decimal value of duty cycle percentage (high time).3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.MOTOROLAA-18ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-7a Expansion Bus Timing (MC68L11E9)VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to THNumCharacteristicSymbolFrequency of Operation (E-Clock Frequency)1.0 MHz2.0 MHzMinMaxMinMaxfodc1.0dc2.0UnitMHz1Cycle Timetcyc1000—500—ns2Pulse Width, E LowPWEL = 1/2 tcyc –25 nsPWEL475—225—ns3Pulse Width, E HighPWEH = 1/2 tcyc –30 nsPWEH470—220—nstrtf——2525——2525nsnstAH95—33—nstAV275—88—nstDSR30—30—ns4A4BE and AS Rise TimeE and AS Fall Time9Address Hold TimetAH = 1/8 tcyc –30 ns(Note 1a)Nonmultiplexed Address Valid Time to E RisetAV = PWEL –(tASD + 80 ns)(Note 1a)1217Read Data Setup Time18Read Data Hold Time (Max = tMAD)tDHR0150088ns19Write Data Delay TimetDDW = 1/8 tcyc + 70 nstDDW—195—133nstDHW95—33—nstAVM265—78—nstASL150—25—nstAHL95—33—nstASD120—58—nsPWASH220—95—nstASED120—58—nstACCA735—298—ns(Note 1a)21Write Data Hold TimetDHW = 1/8 tcyc –30 ns(Note 1a)22Multiplexed Address Valid Time to E RisetAVM = PWEL –(tASD + 90 ns)(Note 1a)24Multiplexed Address Valid Time to AS FalltASL = PWASH –70 ns25Multiplexed Address Hold TimetAHL = 1/8 tcyc –30 ns(Note 1b)Delay Time, E to AS RisetASD = 1/8 tcyc –5 ns(Note 1a)2627Pulse Width, AS HighPWASH = 1/4 tcyc –30 ns28Delay Time, AS to E RisetASED = 1/8 tcyc –5 ns(Note 1b)29MPU Address Access TimetACCA = tcyc –(PWEL–tAVM) –tDSR–tf(Note 1a)35MPU Access TimetACCE = PWEH –tDSRtACCE—440—190ns36Multiplexed Address Delay(Previous Cycle MPU Read)tMAD = tASD + 30 nstMAD150—88—ns(Note 1a)NOTES:1.
Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clockduty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the followingexpressions in place of 1/8 tcyc in the above formulas, where applicable:(a) (1–DC) × 1/4 tcyc(b) DC × 1/4 tcycWhere:DC is the decimal value of duty cycle percentage (high time).2.
All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-19A1234BE4A129R/W, ADDRESS(NON-MUX)2236351729READ18ADDRESSDATAADDRESS/DATA(MULTIPLEXED)19WRITEADDRESS21DATA25A4A244BAS262728NOTE: Measurement points shown are 20% and 70% of VDD.MUX BUS TIMFigure A-14 Multiplexed Expansion Bus Timing DiagramMOTOROLAA-20ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-8 Serial Peripheral Interface TimingVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to THNum1234567CharacteristicSymbol2.0 MHz3.0 MHzMinMaxMinMaxUnitOperating FrequencyMasterSlavefop(m)fop(s)dcdc0.52.0dcdc0.53.0fopMHzCycle TimeMasterSlavetcyc(m)tcyc(s)2.0500——2.0333——tcycnsEnable Lead TimeMaster (Note 2)Slavetlead(m)tlead(s)—250———240——nsnsEnable Lag TimeMaster (Note 2)Slavetlag(m)tlag(s)—250———240——nsnsClock (SCK) High TimeMasterSlavetw(SCKH)mtw(SCKH)s340190——227127——nsnsClock (SCK) Low TimeMasterSlavetw(SCKL)mtw(SCKL)s340190——227127——nsnsData Setup Time (Inputs)MasterSlavetsu(m)tsu(s)100100——100100——nsnsData Hold Time (Inputs)MasterSlaveth(m)th(s)100100——100100——nsns8Access Time (Time to Data Active fromHigh-Impedance State)Slaveta01200120ns9Disable Time (Hold Time to High-Impedance State)Slavetdis—240—167ns10Data Valid (After Enable Edge) (Note 3)tv(s)—240—167ns11Data Hold Time (Outputs) (After Enable Edge)tho0—0—ns12Rise Time (20% VDD to 70% VDD, CL = 200 pF)SPI Outputs (SCK, MOSI, and MISO)SPI Inputs (SCK, MOSI, MISO, and SS)trmtrs——1002.0——1002.0nsµsFall Time (70% VDD to 20% VDD, CL = 200 pF)SPI Outputs (SCK, MOSI, and MISO)SPI Inputs (SCK, MOSI, MISO, and SS)tfmtfs——1002.0——1002.0nsµs131.
All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.2. Signal production depends on software.3. Assumes 200 pF load on SCK, MOSI, and MISO pins.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-21ATable A-8a Serial Peripheral Interface Timing (MC68L11E9)Num1234A5678CharacteristicSymbol1.0 MHz2.0 MHzMinMaxMinMaxUnitOperating FrequencyMasterSlavefop(m)fop(s)dcdc0.51.0dcdc0.52.0fopMHzCycle TimeMasterSlavetcyc(m)tcyc(s)2.01000——2.0500——tcycnsEnable Lead TimeMaster (Note 2)Slavetlead(m)tlead(s)—500———250——nsnsEnable Lag TimeMaster (Note 2)Slavetlag(m)tlag(s)—500———250——nsnsClock (SCK) High TimeMasterSlavetw(SCKH)mtw(SCKH)s680380——340190——nsnsClock (SCK) Low TimeMasterSlavetw(SCKL)mtw(SCKL)s680380——340190——nsnsData Setup Time (Inputs)MasterSlavetsu(m)tsu(s)100100——100100——nsnsData Hold Time (Inputs)MasterSlaveth(m)th(s)100100——100100——nsnsta01200120nsAccess Time(Time to Data Active from High-ImpedanceState)Slave9Disable Time(Hold Time to High-Impedance State)Slavetdis—240—240ns10Data Valid (After Enable Edge) (Note 3)tv(s)—240—240ns11Data Hold Time (Outputs) (After Enable Edge)tho0—0—ns12Rise Time (20% VDD to 70% VDD, CL = 200 pF)SPI Outputs (SCK, MOSI, and MISO)SPI Inputs (SCK, MOSI, MISO, and SS)trmtrs——1002.0——1002.0nsµsFall Time (70% VDD to 20% VDD, CL = 200 pF)SPI Outputs (SCK, MOSI, and MISO)SPI Inputs (SCK, MOSI, MISO, and SS)tfmtfs——1002.0——1002.0nsµs13NOTES:1.
All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.2. Signal production depends on software.3. Assumes 100 pF load on all SPI pins.MOTOROLAA-22ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATASS(INPUT)SS is held high on master.1131213125SCK (CPOL = 0)(OUTPUT)SEENOTE45SCK (CPOL = 1)(OUTPUT)SEENOTE6MISO(INPUT)74MSB INBIT 6 - - - -110 (ref)11MOSI(OUTPUT)MASTER MSB OUTLSB IN1011 (ref)BIT 6 - - - -1MASTER LSB OUT1312NOTE: This first clock edge is generated internally but is not seen at the SCK pin.SPI MASTER CPHA0 TIMAa) SPI Master Timing (CPHA = 0)SS(INPUT)SS is held high on master.1135SCK (CPOL = 0)(OUTPUT)12SEENOTE4135SCK (CPOL = 1)(OUTPUT)SEENOTE4MISO(INPUT)12MSB IN10 (ref)MOSI(OUTPUT)6BIT 6 - - - -111MASTER MSB OUT7LSB IN10BIT 6 - - - -111 (ref)MASTER LSB OUT13NOTE: This last clock edge is generated internally but is not seen at the SCK pin.12SPI MASTER CPHA1 TIMb) SPI Master Timing (CPHA = 1)Figure A-15 SPI Timing Diagram (1 of 2)M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-23SS(INPUT)11312121335SCK (CPOL = 0)(INPUT)425SCK (CPOL = 1)(INPUT)48MISO(OUTPUT)6MOSI(INPUT)BIT 6 - - - -1MSB OUTSLAVE710SEENOTESLAVE LSB OUT1111BIT 6 - - - -1MSB IN9LSB INNOTE: Not defined but normally MSB of character just received.ASPI SLAVE CPHA0 TIMa) SPI Slave Timing (CPHA = 0)SS(INPUT)112135SCK (CPOL = 0)(INPUT)4235SCK (CPOL = 1)(INPUT)8MISO(OUTPUT)410SEENOTESLAVEMSB OUT6MOSI(INPUT)7MSB IN1312BIT 6 - - - -1109SLAVE LSB OUT11BIT 6 - - - -1LSB INNOTE: Not defined but normally LSB of character previously transmitted.SPI SLAVE CPHA1 TIMb) SPI Slave Timing (CPHA = 1)Figure A-15 SPI Timing Diagram (2 of 2)MOTOROLAA-24ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-9 EEPROM CharacteristicsVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to THCharacteristicTemperature RangeUnit–40 to 85°C–40 to 105°C–40 to 125°CProgramming Time<1.0 MHz, RCO Enabled(Note 1)1.0 to 2.0 MHz, RCO Disabled≥2.0 MHz (or Anytime RCO Enabled)10201015Must use RCO1520Must use RCO20msErase Time (Note 1)101010ms10,00010,00010,000Cycles101010YearsByte, Row and BulkWrite/Erase Endurance (Note 2)Data Retention (Note 2)NOTES:1.
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