Микроконтроллер Motorola 68HC11 (1086181), страница 22
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To enable it as an input capture pin, set theI4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To useit as an output compare register, set the I4/O5 bit to a logic level zero. Refer to 9.6Pulse Accumulator.TI4/O5 — Timer Input Capture 4/Output Compare 5$101E$101FBit 15Bit 7146135124113$101E, $101F10291Bit 8Bit 0TI4/O5 (High)TI4/O5 (Low)The TI4/O5 register pair resets to ones ($FFFF).MOTOROLA9-6TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATA9.3 Output CompareUse the output compare (OC) function to program an action to occur at a specific time— when the 16-bit counter reaches a specified value. For each of the five output compare functions, there is a separate 16-bit compare register and a dedicated 16-bit comparator. The value in the compare register is compared to the value of the free-runningcounter on every bus cycle.
When the compare register matches the counter value, anoutput compare status flag is set. The flag can be used to initiate the automatic actionsfor that output compare function.To produce a pulse of a specific duration, write a value to the output compare registerthat represents the time the leading edge of the pulse is to occur. The output comparecircuit is configured to set the appropriate output either high or low, depending on thepolarity of the pulse being produced. After a match occurs, the output compare registeris reprogrammed to change the output pin back to its inactive level at the next match.A value representing the width of the pulse is added to the original value, and then written to the output compare register.
Because the pin state changes occur at specificvalues of the free-running counter, the pulse width can be controlled accurately at theresolution of the free-running counter, independent of software latencies. To generatean output signal of a specific frequency and duty cycle, repeat this pulse-generatingprocedure.There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, andTOC4, and the TI4/O5 register, which functions under software control as either IC4or OC5. Each of the OC registers is set to $FFFF on reset. A value written to an OCregister is compared to the free-running counter value during each E-clock cycle. If amatch is found, the particular output compare flag is set in timer interrupt flag register1 (TFLG1).
If that particular interrupt is enabled in the timer interrupt mask register 1(TMSK1), an interrupt is generated. In addition to an interrupt, a specified action canbe initiated at one or more timer output pins. For OC[5:2], the pin action is controlledby pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken oneach successful compare, regardless of whether or not the OCxF flag in the TFLG1register was previously cleared.OC1 is different from the other output compares in that a successful OC1 compare canaffect any or all five of the OC pins.
The OC1 output action taken when a match isfound is controlled by two 8-bit registers with three bits unimplemented: the outputcompare 1 mask register, OC1M, and the output compare 1 data register, OC1D.OC1M specifies which port A outputs are to be used, and OC1D specifies what datais placed on these port pins.9.3.1 Timer Output Compare RegistersAll output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset.If an output compare register is not used for an output compare function, it can be usedas a storage location. A write to the high-order byte of an output compare register pairinhibits the output compare function for one bus cycle.
This inhibition prevents inappropriate subsequent comparisons. Coherency requires a complete 16-bit read orwrite. However, if coherency is not needed, byte accesses can be used.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-79For output compare functions, write a comparison value to output compare registersTOC1 – TOC4 and TI4/O5. When TCNT value matches the comparison value, specified pin actions occur.TOC1 – TOC4 — Timer Output Compare9$1016 – $101D$1016$1017Bit 15Bit 714613512411310291Bit 8Bit 0TOC1 (High)TOC1 (Low)$1018$1019Bit 15Bit 714613512411310291Bit 8Bit 0TOC2 (High)TOC2 (Low)$101A$101BBit 15Bit 714613512411310291Bit 8Bit 0TOC3 (High)TOC3 (Low)$101C$101DBit 15Bit 714613512411310291Bit 8Bit 0TOC4 (High)TOC4 (Low)All TOCx register pairs reset to ones ($FFFF).9.3.2 Timer Compare Force RegisterThe CFORC register allows forced early compares.
FOC[1:5] correspond to the fiveoutput compares. These bits are set for each output compare that is to be forced. Theaction taken as a result of a forced compare is the same as if there were a match between the OCx register and the free-running counter, except that the correspondinginterrupt status flag bits are not set. The forced channels trigger their programmed pinactions to occur at the next timer count transition after the write to CFORC.The CFORC bits should not be used on an output compare function that is programmed to toggle its output on a successful compare because a normal compare thatoccurs immediately before or after the force can result in an undesirable operation.CFORC — Timer Compare ForceRESET:Bit 7FOC106FOC20$100B5FOC304FOC403FOC502—01—0Bit 0—0FOC[1:5] — Force Output ComparisonWhen the FOC bit associated with an output compare circuit is set, the output comparecircuit immediately performs the action it is programmed to do when an output matchoccurs.0 = Not affected1 = Output x action occursBits [2:0] — Not implementedAlways read zeroMOTOROLA9-8TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATA9.3.3 Output Compare Mask RegisterUse OC1M with OC1 to specify the bits of port A that are affected by a successful OC1compare.
The bits of the OC1M register correspond to PA[7:3].OC1M — Output Compare 1 MaskRESET:Bit 7OC1M706OC1M60$100C5OC1M504OC1M403OC1M302—01—0Bit 0—0OC1M[7:3] — Output Compare Masks0 = OC1 is disabled.1 = OC1 is enabled to control the corresponding pin of port ABits [2:0] — Not implementedAlways read zero.9.3.4 Output Compare Data RegisterUse this register with OC1 to specify the data that is to be stored on the affected pinof port A after a successful OC1 compare. When a successful OC1 compare occurs,a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set inOC1M.OC1D — Output Compare 1 DataRESET:Bit 7OC1D706OC1D60$100D5OC1D504OC1D403OC1D302—01—0Bit 0—0If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.Bits [2:0] — Not implementedAlways read zero9.3.5 Timer Counter RegisterThe 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer.
Afull counter read addresses the most significant byte (MSB) first. A read of this addresscauses the least significant byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state of the counter at the time ofthe MSB read cycle.TCNT — Timer Counter$100E$100FBit 15Bit 7146$100E, $100F13512411310291Bit 8Bit 0TCNT (High)TCNT (Low)TCNT resets to $0000. In normal modes, TCNT is read-only.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-999.3.6 Timer Control Register 1The bits of this register specify the action taken as a result of a successful OCx compare.TCTL1 — Timer Control 1RESET:Bit 7OM20$10206OL205OM304OL303OM402OL401OM50Bit 0OL50OM[2:5] — Output ModeOL[2:5] — Output LevelThese control bit pairs are encoded to specify the action taken after a successful OCxcompare.
OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer toTable 9-3 for the coding.9Table 9-3 Timer Output Compare ActionsOMxOLxAction Taken on Successful Compare00Timer disconnected from output pin logic01Toggle OCx output line10Clear OCx output line to zero11Set OCx output line to one9.3.7 Timer Interrupt Mask Register 1Use this 8-bit register to enable or inhibit the timer input capture and output compareinterrupts.TMSK1 — Timer Interrupt Mask 1RESET:Bit 7OC1I06OC2I0$10225OC3I04OC4I03I4/O5I02IC1I01IC2I0Bit 0IC3I0OC1I – OC4I — Output Compare x Interrupt EnableIf the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.I4/O5I — Input Capture 4/Output Compare 5 Interrupt EnableWhen I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit.
WhenI4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.IC1I – IC3I — Input Capture x Interrupt EnableIf the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequenceis requested.MOTOROLA9-10TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATANOTEBits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones inTMSK1 enable the corresponding interrupt sources.9.3.8 Timer Interrupt Flag Register 1Bits in this register indicate when timer system events have occurred.
Coupled withthe bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either apolled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 inthe same position.TFLG1 — Timer Interrupt Flag 1RESET:Bit 7OC1F06OC2F0$10235OC3F04OC4F03I4/O5F02IC1F01IC2F0Bit 0IC3F09Clear flags by writing a one to the corresponding bit position(s).OC1F – OC4F — Output Compare x FlagSet each time the counter matches output compare x valueI4/O5F — Input Capture 4/Output Compare 5 FlagSet by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTLIC1F – IC3F — Input Capture x FlagSet each time a selected active edge is detected on the ICx input line9.3.9 Timer Interrupt Mask Register 2Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts.
Thetimer prescaler control bits are included in this register.TMSK2 — Timer Interrupt Mask 2RESET:Bit 7TOI06RTII0$10245PAOVI04PAII03—02—01PR10Bit 0PR00TOI — Timer Overflow Interrupt Enable0 = TOF interrupts disabled1 = Interrupt requested when TOF is set to oneRTII — Real-Time Interrupt EnableRefer to 9.4 Real-Time Interrupt.PAOVI — Pulse Accumulator Overflow Interrupt EnableRefer to 9.6.3 Pulse Accumulator Status and Interrupt Bits.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-11PAII — Pulse Accumulator Input Edge Interrupt EnableRefer to 9.6.3 Pulse Accumulator Status and Interrupt Bits.Bits [3:2] — Not implementedAlways read zeroPR[1:0] — Timer Prescaler SelectThese bits are used to select the prescaler divide-by ratio.
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