Микроконтроллер Motorola 68HC11 (1086181), страница 21
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At the completion of transferring a byte of data, the SPIF status bit isset in both the master and slave devices.M68HC11 E SERIESTECHNICAL DATASERIAL PERIPHERAL INTERFACEMOTOROLA8-78A read of the SPDR is actually a read of a buffer. To prevent an overrun and the lossof the byte that caused the overrun, the first SPIF must be cleared by the time a secondtransfer of data from the shift register to the read buffer is initiated.SPDR — SPI Data RegisterBit 7Bit 766$102A5544332211Bit 0Bit 0SPI is double buffered in and single buffered out.8MOTOROLA8-8SERIAL PERIPHERAL INTERFACEM68HC11 E SERIESTECHNICAL DATASECTION 9 TIMING SYSTEMThe M68HC11 timing system is composed of five clock divider chains. The main clockdivider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler.
The main timer’s programmable prescaler provides one of the fourclocking rates to drive the 16-bit counter. Two prescaler control bits select the prescalerate.The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this mainclocking chain drive circuitry that generates the slower clocks used by the pulse accumulator, the real-time interrupt (RTI), and the computer operating properly (COP)watchdog subsystems, also described in this section.
Refer to Figure 9-1.All main timer system activities are referenced to this free-running counter. Thecounter begins incrementing from $0000 as the MCU comes out of reset, and continues to the maximum count, $FFFF. At the maximum count, the counter rolls over to$0000, sets an overflow flag, and continues to increment. As long as the MCU is running in a normal operating mode, there is no way to reset, change, or interrupt thecounting. The capture/compare subsystem features three input capture channels, fouroutput compare channels, and one channel that can be selected to perform either input capture or output compare.
Each of the three input capture functions has its own16-bit input capture register (time capture latch) and each of the output compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors.The pulse accumulator contains an 8-bit counter and edge select logic. The pulse accumulator can operate in either event counting mode or gated time accumulationmode. During event counting mode, the pulse accumulator’s 8-bit counter incrementswhen a specified edge is detected on an input signal. During gated time accumulationmode, an internal clock source increments the 8-bit counter while an input signal hasa predetermined logic level.The real-time interrupt (RTI) is a programmable periodic interrupt circuit that permitspacing the execution of software routines by selecting one of four interrupt rates.The COP watchdog clock input (E ÷ 215) is tapped off of the free-running counterchain.
The COP automatically times out unless it is serviced within a specific time bya program reset sequence. If the COP is allowed to time out, a reset is generated,which drives the RESET pin low to reset the MCU and the external system. Refer toTable 9-1 for crystal related frequencies and periods.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-19OSCILLATOR ANDCLOCK GENERATOR(DIVIDE BY FOUR)ASE CLOCKINTERNAL BUS CLOCK (PH2)PRESCALER(÷ 2, 4, 16, 32)SPR[1:0]PRESCALER(÷ 1, 3, 4, 13)SCP[1:0]SPIPRESCALER(÷ 1, 2, 4,....128)SCR[2:0]÷ 39SCP2*SCI RECEIVER CLOCK÷16E÷26PULSE ACCUMULATORPRESCALER(÷ 1, 2, 4, 8)RTR[1:0]E÷2139SCI TRANSMIT CLOCK÷4PRESCALER(÷ 1, 4, 8, 16)PR[1:0]REAL-TIME INTERRUPTE÷215PRESCALER(÷1, 4, 16, 64)CR[1:0]TOFTCNTFF1FF2SQRQSQRQFORCECOPRESETIC/OC* SCP2 PRESENT ON MC68HC(7)11E20 ONLY.CLEAR COPTIMERSYSTEMRESETE SERIES TIM DIV CHAINFigure 9-1 Timer Clock Divider ChainsMOTOROLA9-2TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATATable 9-1 Timer SummaryXTAL FrequenciesControl BitsPR1, PR04.0 MHz8.0 MHz12.0 MHzOther Rates1.0 MHz2.0 MHz3.0 MHz(E)1000 ns500 ns333 ns(1/E)Main Timer Count Rates001 count —overflow —1000 ns65.536 ms500 ns32.768 ms333 ns21.845 ms(E/1)(E/216)011 count —overflow —4.0 µs262.14 ms2.0 µs131.07 ms1.333 µs87.381 ms(E/4)(E/218)101 count —overflow —8.0 µs524.29 ms4.0 µs262.14 ms2.667 µs174.76 ms(E/8)(E/219)111 count —overflow —16.0 µs1.049 s8.0 µs524.29 ms5.333 µs349.52 ms(E/16)(E/220)9.1 Timer StructureFigure 9-2 shows the capture/compare system block diagram.
The port A pin controlblock includes logic for timer functions and for general-purpose I/O. For pins PA3,PA2, PA1, and PA0, this block contains both the edge-detection logic and the controllogic that enables the selection of which edge triggers an input capture. The digital level on PA[3:0] can be read at any time (read PORTA register), even if the pin is beingused for the input capture function. Pins PA[6:3] are used for either general-purposeI/O, or as output compare pins. When one of these pins is being used for an outputcompare function, it cannot be written directly as if it were a general-purpose output.Each of the output compare functions (OC[5:2]) is related to one of the port A outputpins. Output compare one (OC1) has extra control logic, allowing it optional control ofany combination of the PA[7:3] pins.
The PA7 pin can be used as a general-purposeI/O pin, as an input to the pulse accumulator, or as an OC1 output pin.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-39MCUE CLKPRESCALERDIVIDE BY1, 4, 8, OR 16PR1TCNT (HI)TCNT (LO)TOI16-BIT FREE RUNNINGCOUNTERPR09TOFTAPS FOR RTI,COP WATCHDOG, ANDPULSE ACCUMULATOR16-BIT TIMER BUSINTERRUPT REQUESTS(FURTHER QUALIFIED BYI BIT IN CCR)TO PULSEACCUMULATOROC1I16-BIT COMPARATOR =TOC1 (HI)OC1FTOC1 (LO)FOC1OC2I16-BIT COMPARATOR =TOC2 (HI)9TOC2 (LO)TOC3 (LO)TOC4 (LO)OC5TI4/O5 (LO)I4/O5FCLKTIC2 (HI)TIC3 (HI)PA4/OC4/OC1BIT 3PA3/OC5/IC4/OC1BIT 2PA2/IC1BIT 1PA1/IC2BIT 0PA0/IC34FOC5CFORCFORCE OUTPUTCOMPARECLKIC1ICLKIC2I2IC2FTIC2 (LO)CLK3IC1FTIC1 (LO)16-BIT LATCHBIT 4IC4I4/O516-BIT LATCHPA5/OC3/OC15FOC416-BIT COMPARATOR =16-BIT LATCHBIT 5OC4FI4/O5ITIC1 (HI)PA6/OC2/OC16FOC316-BIT COMPARATOR =16-BIT LATCHBIT 6OC3FOC4ITI4/O5 (HI)PA7/OC1/PAI7FOC216-BIT COMPARATOR =TOC4 (HI)BIT 7OC2FOC3ITOC3 (HI)PINFUNCTIONS8IC3IIC3F1TIC3 (LO)TFLG 1STATUSFLAGSTMSK 1INTERRUPTENABLESPORT APIN CONTROLCAPTURE COMPARE BLOCKFigure 9-2 Capture/Compare Block Diagram9.2 Input CaptureThe input capture function records the time an external event occurs by latching thevalue of the free-running counter when a selected edge is detected at the associatedtimer input pin.
Software can store latched values and use them to compute the periodicity and duration of events. For example, by storing the times of successive edgesof an incoming signal, software can determine the period and pulse width of a signal.MOTOROLA9-4TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATATo measure period, two successive edges of the same polarity are captured. To measure pulse width, two alternate polarity edges are captured.In most cases, input capture edges are asynchronous to the internal timer counter,which is clocked relative to an internal clock (PH2).
These asynchronous capture requests are synchronized to PH2 so that the latching occurs on the opposite half cycleof PH2 from when the timer counter is being incremented. This synchronization process introduces a delay from when the edge occurs to when the counter value is detected. Because these delays offset each other when the time between two edges isbeing measured, the delay can be ignored. When an input capture is being used withan output compare, there is a similar delay between the actual compare point andwhen the output pin changes state.The control and status bits that implement the input capture functions are contained inthe PACTL, TCTL2, TMSK1, and TFLG1 registers.To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register.
Note that this bit is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifthoutput compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on thepin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 registeris acting as IC4.9.2.1 Timer Control Register 2Use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. Each of the input capturefunctions can be independently configured to detect rising edges only, falling edgesonly, any edge (rising or falling), or to disable the input capture function.
The input capture functions operate independently of each other and can capture the same TCNTvalue if the input edges are detected within the same timer count cycle.TCTL2 — Timer Control 2RESET:Bit 7EDG4B06EDG4A0$10215EDG1B04EDG1A03EDG2B02EDG2A01EDG3B0Bit 0EDG3A0EDGxB and EDGxA — Input Capture Edge ControlThere are four pairs of these bits. Each pair is cleared to zero by reset and must beencoded to configure the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL register is set.
Refer to Table 9-2 for timer control configuration.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-59Table 9-2 Timer Control Configuration9EDGxBEDGxAConfiguration00Capture disabled01Capture on rising edges only10Capture on falling edges only11Capture on any edge9.2.2 Timer Input Capture RegistersWhen an edge has been detected and synchronized, the 16-bit free-running countervalue is transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and timer counter incrementing occur on oppositehalf-cycles of the phase 2 clock so that the count value is stable whenever a captureoccurs. The TICx registers are not affected by reset.
Input capture values can be readfrom a pair of 8-bit read-only registers. A read of the high-order byte of an input captureregister pair inhibits a new capture transfer for one bus cycle. If a double-byte read instruction, such as LDD, is used to read the captured value, coherency is assured.When a new input capture occurs immediately after a high-order byte read, transfer isdelayed for an additional cycle but the value is not lost.TIC1 – TIC3 — Timer Input Capture$1010 – $1015$1010$1011Bit 15Bit 714613512411310291Bit 8Bit 0TIC1 (High)TIC1 (Low)$1012$1013Bit 15Bit 714613512411310291Bit 8Bit 0TIC2 (High)TIC2 (Low)$1014$1015Bit 15Bit 714613512411310291Bit 8Bit 0TIC3 (High)TIC3 (Low)TICx not affected by reset.9.2.3 Timer Input Capture 4/Output Compare 5 RegisterUse TI4/O5 as either an input capture register or an output compare register, depending on the function chosen for the PA3 pin.
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