Микроконтроллер Motorola 68HC11 (1086181), страница 17
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STRA is an edge-detecting input and STRB is a handshake output. Controland enable bits are located in the PIOC register.In full input handshake mode, the MCU asserts STRB to signal an external system thatit is ready to latch data. Port C logic levels are latched into PORTCL when the STRAMOTOROLA6-4PARALLEL INPUT/OUTPUTM68HC11 E SERIESTECHNICAL DATAline is asserted by the external system. The MCU then negates STRB. The MCU reasserts STRB after the PORTCL register is read. In this mode, a mix of latched inputs,static inputs, and static outputs is allowed on port C, differentiated by the data directionbits and use of the PORTC and PORTCL registers.In full output handshake mode, the MCU writes data to PORTCL which, in turn, assertsthe STRB output to indicate that data is ready.
The external system reads port C dataand asserts the STRA input to acknowledge that data has been received.In the three-state variation of output handshake mode, lines intended as three-statehandshake outputs are configured as inputs by clearing the corresponding DDRC bits.The MCU writes data to PORTCL and asserts STRB. The external system respondsby activating the STRA input, which forces the MCU to drive the data in PORTC outon all of the port C lines.
After the trailing edge of the active signal on STRA, the MCUnegates the STRB signal. The three-state mode variation does not allow part of portC to be used for static inputs while other port C pins are being used for handshakeoutputs. Refer to the PIOC register description for further information.6.7 Parallel I/O Control RegisterThe parallel handshake functions are available only in the single-chip operating mode.PIOC is a read/write register except for bit 7, which is read only. Table 6-2 shows asummary of handshake operations.PIOC — Parallel I/O ControlRESET:Bit 7STAF06STAI0$10025CWOM04HNDS03OIN02PLSU1EGA1Bit 0INVB1STAF — Strobe A Interrupt Status Flag0 = No edge on strobe A1 = Selected edge on strobe ASTAF is set when the selected edge occurs on strobe A.
This bit can be cleared by aread of PIOC with STAF set followed by a read of PORTCL (simple strobed or full inputhandshake mode) or a write to PORTCL (output handshake mode).STAI — Strobe A Interrupt Enable Mask0 = STAF does not request interrupt1 = STAF requests interruptCWOM — Port C Wired-OR Mode (affects all eight port C pins)It is customary to have an external pull-up resistor on lines that are driven by opendrain devices.0 = Port C outputs are normal CMOS outputs1 = Port C outputs are open-drain outputsM68HC11 E SERIESTECHNICAL DATAPARALLEL INPUT/OUTPUTMOTOROLA6-56HNDS — Handshake Mode0 = Simple strobe mode1 = Full input or output handshake modeOIN — Output or Input Handshake SelectHNDS must be set to one for this bit to have meaning.0 = Input handshake1 = Output handshakePLS — Pulsed/Interlocked Handshake OperationHNDS must be set to one for this bit to have meaning.
When interlocked handshakeis selected, strobe B is active until the selected edge of strobe A is detected.0 = Interlocked handshake1 = Pulsed handshake (strobe B pulses high for two E-clock cycles.)6EGA — Active Edge for Strobe A0 = STRA falling edge selected, high level activates port C outputs (output handshake)1 = STRA rising edge selected, low level activates port C outputs (output handshake)INVB — Invert Strobe B0 = Active level is logic zero1 = Active level is logic oneTable 6-2 Parallel I/O ControlSimpleStrobedModeFull inputHandshakemodeFull outputhandshakemodeSTAFClearingSequenceRead PIOCwith STAF= 1 thenreadPORTCLHNDSOINPLS0XX0Port BPort CInputs latched intoPORTCL on anyactive edge onSTRASTRB pulses onwrites to PORTB1Read PIOCwith STAF= 1 thenreadPORTCL1read PIOCwith STAF= 1 thenwritePORTCL1MOTOROLA6-6EGA00 = STRBactive level1 = STRBactive pulse1Inputs latched intoNormal outputPORTCL on any port, unaffected inactive edge onhandshakeSTRAmodes010 = STRBactive level1 = STRBactive pulse0Port CDrivenSTRAFollow Active Edge FollowDDRCDDRC1PARALLEL INPUT/OUTPUTDriven as outputsNormal outputif STRA at active port, unaffected inlevel; followshandshakeDDRC if STRAmodesnot at active levelM68HC11 E SERIESTECHNICAL DATASECTION 7 SERIAL COMMUNICATIONS INTERFACEThe serial communications interface (SCI) is a universal asynchronous receiver transmitter (UART), one of two independent serial I/O subsystems in the M68HC11 E seriesof microcontrollers.
It has a standard nonreturn to zero (NRZ) format (one start, eightor nine data, and one stop bit). Several baud rates are available. The SCI transmitterand receiver are independent, but use the same data format and bit rate.All members of the E series contain the same SCI, with one exception. The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs has an enhanced SCI baudrate generator.
A divide-by-39 stage has been added that is enabled by an extra bit inthe BAUD register. This increases the available SCI baud rate selections. Refer to thebaud rate generator diagrams and the BAUD register description.7.1 Data FormatThe serial data format requires the following conditions:1. An idle-line in the high state before transmission or reception of a message.2.
A start bit, logic zero, transmitted or received, that indicates the start of eachcharacter.3. Data that is transmitted and received least significant bit (LSB) first.4. A stop bit, logic one, used to indicate the end of a frame. (A frame consists of astart bit, a character of eight or nine data bits, and a stop bit.)5. A break (defined as the transmission or reception of a logic zero for some multiple number of frames).Selection of the word length is controlled by the M bit of SCI control register SCCR1.7.2 Transmit OperationThe SCI transmitter includes a parallel transmit data register (SCDR) and a serial shiftregister. The contents of the serial shift register can only be written through the SCDR.This double buffered operation allows a character to be shifted out serially while another character is waiting in the SCDR to be transferred into the serial shift register.The output of the serial shift register is applied to TxD as long as transmission is inprogress or the transmit enable (TE) bit of serial communication control register 2(SCCR2) is set.
The block diagram, Figure 7-1, shows the transmit serial shift register,and the buffer logic at the top of the figure.M68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-17(WRITE ONLY)TRANSMITTERBAUD RATECLOCKSCDR Tx BUFFERDDD110 (11) - BIT Tx SHIFT REGISTER210PIN BUFFERAND CONTROLLBREAKÑJAM 0s3PREAMBLEÑJAM 1s4JAM ENABLE5SHIFT ENABLE6TRANSFER Tx BUFFERSIZE 8/9H (8) 7PD1TxD8FORCE PINDIRECTION (OUT)TRANSMITTERCONTROL LOGIC7TDRETCRDRFIDLEORNFFEMWAKER8T88SCSR INTERRUPT STATUSSCCR1 SCI CONTROL 18TDRETIETIETCIERIEILIETERERWUSBKTCTCIESCCR2 SCI CONTROL 2SCI RxREQUESTSSCI INTERRUPTREQUESTINTERNALDATA BUSSCI TX BLOCK 2Figure 7-1 SCI Transmitter Block DiagramMOTOROLA7-2SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATA7.3 Receive OperationDuring receive operations, the transmit sequence is reversed. The serial shift registerreceives data and transfers it to a parallel receive data register (SCDR) as a completeword.
This double buffered operation allows a character to be shifted in serially whileanother character is already in the SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectivelysampled to detect receive data, and a majority voting circuit determines the value andintegrity of each bit.7M68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-3RECEIVERBAUD RATECLOCKPIN BUFFERAND CONTROLPD0RxD10 (11) - BITRx SHIFT REGISTERSTOP÷16DATARECOVERYSTARTDDD0(8) 76543210MSBDISABLEDRIVERALL ONESREM7WAKEUPLOGICRWUTDRETCRDRFIDLEORNFFEMWAKER8T88SCCR1 SCI CONTROL 1SCSR SCI STATUS 1SCDR Rx BUFFER(READ ONLY)8RDRFRIEIDLEILIETIETCIERIEILIETERERWUSBKORRIE8SCCR2 SCI CONTROL 2SCI TxREQUESTSSCI INTERRUPTREQUESTINTERNALDATA BUSSCI RX BLOCK 2Figure 7-2 SCI Receiver Block DiagramMOTOROLA7-4SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATA7.4 Wakeup FeatureThe wakeup feature reduces SCI service overhead in multiple receiver systems.
Software for each receiver evaluates the first character of each message. The receiver isplaced in wakeup mode by writing a one to the RWU bit in the SCCR2 register. WhileRWU is one, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) areinhibited (cannot become set). Although RWU can be cleared by a software write toSCCR2, to do so would be unusual. Normally RWU is set by software and is clearedautomatically with hardware.
Whenever a new message begins, logic alerts the sleeping receivers to wake up and evaluate the initial character of the new message.Two methods of wakeup are available: idle-line wakeup and address-mark wakeup.During idle-line wakeup, a sleeping receiver awakens as soon as the RxD line becomes idle. In the address-mark wakeup, logic one in the most significant bit (MSB) ofa character wakes up all sleeping receivers.7.4.1 Idle-Line WakeupTo use the receiver wakeup method, establish a software addressing scheme to allowthe transmitting devices to direct a message to individual receivers or to groups of receivers.
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