Микроконтроллер Motorola 68HC11 (1086181), страница 13
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The procedure for programming is thesame as for programming a byte in the EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed or erased (including byte erase)while the MCU is operating in any mode, provided that PTCON in BPROT is clear. Tochange the value in the CONFIG register, complete the following procedure. Do notinitiate a reset until the procedure is complete.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-2341. Erase the CONFIG register.2.
Program the new value to the CONFIG address.3. Initiate reset.4.4.2 EEPROM SecurityThe optional security feature, available only on ROM-based MCUs, protects the EEPROM and RAM contents from unauthorized access. A program, or a key portion of aprogram, can be protected against unauthorized duplication. To accomplish this, theprotection mechanism restricts operation of protected devices to the single-chipmodes. This prevents the memory locations from being monitored externally becausesingle-chip modes do not allow visibility of the internal address and data buses.
Resident programs, however, have unlimited access to the internal EEPROM and RAMand can read, write, or transfer the contents of these memories.4An enhanced security feature which protects EPROM contents, RAM, and EEPROMfrom unauthorized accesses is available in MC68S711E9. Refer to APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION for the exact part number.MOTOROLA4-24OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATASECTION 5 RESETS AND INTERRUPTSResets and interrupt operations load the program counter with a vector that points toa new location from which instructions are to be fetched.
A reset immediately stopsexecution of the current instruction and forces the program counter to a known startingaddress. Internal registers and control bits are initialized so the MCU can resume executing instructions. An interrupt temporarily suspends normal program executionwhile an interrupt service routine is being executed.
After an interrupt has been serviced, the main program resumes as if there had been no interruption.5.1 ResetsThere are four possible sources of reset. Power-on reset (POR) and external resetshare the normal reset vector. The computer operating properly (COP) reset and theclock monitor reset each has its own vector.5.1.1 Power-On ResetA positive transition on VDD generates a power-on reset (POR), which is used only forpower-up conditions. POR cannot be used to detect drops in power supply voltages.A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active allows theclock generator to stabilize. If RESET is at logical zero at the end of 4064 tcyc, the CPUremains in the reset condition until RESET goes to logical one.It is important to protect the MCU during power transitions. Most M68HC11 systemsneed an external circuit that holds the RESET pin low whenever VDD is below the minimum operating level.
This external voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internalcircuitry during cold starts. Refer to Figure 2-3.5.1.2 External Reset (RESET)The CPU distinguishes between internal and external reset conditions by sensingwhether the reset pin rises to a logic one in less than two E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is drivenlow by an internal device for four E-clock cycles, then released. Two E-clock cycleslater it is sampled. If the pin is still held low, the CPU assumes that an external resethas occurred.
If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor. Do not connect an external resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices because thecircuit charge time constant can cause the device to misinterpret the type of reset thatoccurred.5.1.3 COP ResetThe MCU includes a COP system to help protect against software failures. When theCOP is enabled, the software is responsible for keeping a free-running watchdog timerM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-15from timing out. When the software is no longer being executed in the intended sequence, a system reset is initiated.The state of the NOCOP bit in the CONFIG register determines whether the COP system is enabled or disabled. To change the enable status of the COP system, changethe contents of the CONFIG register and then perform a system reset.
In the specialtest and bootstrap operating modes, the COP system is initially inhibited by the disableresets (DISR) control bit in the TEST1 register. The DISR bit can subsequently be written to zero to enable COP resets.The COP timer rate control bits CR[1:0] in the OPTION register determine the COPtimeout period. The system E clock is divided by 215 and then further scaled by a factor shown in Table 5-1.
After reset, these bits are zero, which selects the fastest timeout period. In normal operating modes, these bits can only be written once within 64bus cycles after reset.5Table 5-1 COP Timer Rate SelectCR[1:0]DivideE/215 By0001XTAL = 4.0 MHzTimeout– 0 ms, + 32.8 msXTAL = 8.0 MHzTimeout– 0 ms, + 16.4 msXTAL = 12.0 MHzTimeout– 0 ms, + 10.9 ms132.768 ms16.384 ms10.923 ms4131.072 ms65.536 ms43.691 ms1016524.28 ms262.14 ms174.76 ms11642.098 s1.049 s699.05 msE=1.0 MHz2.0 MHz3.0 MHzCOPRST — Arm/Reset COP Timer CircuitryRESET:Bit 770660550440$103A330220110Bit 000Complete the following reset sequence to service the COP timer.
Write $55 to COPRST to arm the COP timer clearing mechanism. Then write $AA to COPRST to clearthe COP timer. Performing instructions between these two steps is possible as longas both steps are completed in the correct sequence before the timer times out.5.1.4 Clock Monitor ResetThe clock monitor circuit is based on an internal RC time delay. If no MCU clock edgesare detected within this RC time delay, the clock monitor can optionally generate a system reset.
The clock monitor function is enabled or disabled by the CME control bit inthe OPTION register. The presence of a timeout is determined by the RC delay, whichallows the clock monitor to operate without any MCU clocks.Clock monitor is used as a backup for the COP system. Because the COP needs aclock to function, it is disabled when the clocks stop. Therefore, the clock monitor system can detect clock failures not detected by the COP system.MOTOROLA5-2RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATASemiconductor wafer processing causes variations of the RC timeout values betweenindividual devices.
An E-clock frequency below 10 kHz is detected as a clock monitorerror. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Usingthe clock monitor function when the E-clock is below 200 kHz is not recommended.Special considerations are needed when a STOP instruction is executed and the clockmonitor is enabled.
Because the STOP function causes the clocks to be halted, theclock monitor function generates a reset sequence if it is enabled at the time the STOPmode was initiated. Before executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock monitor. After recovery from STOP, set theCME bit to logic one to enable the clock monitor. Alternatively, executing a STOP instruction with the CME bit set to logic one can be used as a software initiated reset.5.1.5 Option RegisterOPTION — System Configuration OptionsRESET:Bit 7ADPU6CSEL5IRQE1000$10394DLY113CME2—001Bit 0CR110CR010NOTES:1. Can be written only once in first 64 cycles out of reset in normal modes, or at any time in specialmodes.ADPU — Analog-to-Digital Converter Power-UpRefer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.CSEL — Clock SelectRefer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.IRQE — Configure IRQ for Edge-Sensitive Only Operation0 = IRQ is configured for level-sensitive operation1 = IRQ is configured for edge-sensitive only operationDLY — Enable Oscillator Startup DelayRefer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY and SECTION10 ANALOG-TO-DIGITAL CONVERTER.CME — Clock Monitor EnableThis control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system clock is slow orabsent.
When it is clear, the clock monitor circuit is disabled, and when it is set, theclock monitor circuit is enabled. Reset clears the CME bit.0 = Clock monitor circuit disabled1 = Slow or stopped clocks cause resetBit 2 — Not implementedAlways reads zeroM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-35CR[1:0] — COP Timer Rate SelectThe internal E clock is first divided by 215 before it enters the COP watchdog system.These control bits determine a scaling factor for the watchdog timer.5.1.6 CONFIG RegisterCONFIG — Configuration Control RegisterRESET:Bit 7EE3*06EE2*05EE1*04EE0*0$103F3NOSEC12NOCOP11ROMON1Bit 0EEON1EE[3:0] — EEPROM Mapping*EE[3:0] apply only to MC68HC811E2.
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