Микроконтроллер Motorola 68HC11 (1086181), страница 11
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The contents of the EEPROM byte are transferredinto static working latches during reset sequences. The operation of the MCU is controlled directly by these latches and not by CONFIG itself. In normal modes, changesto CONFIG do not affect operation of the MCU until after the next reset sequence.When programming, the CONFIG register itself is accessed. When the CONFIG register is read, the static latches are accessed.Operation of the CONFIG register in the MC68HC811E2 differs from other devices inthe M68HC11 E series. Refer to the two descriptions of the CONFIG register.CONFIG — System ConfigurationRESETS:S.
Chip:Boot:Exp.:Test:MOTOROLA4-12$103FBit 7—6—5—4—3NOSEC2NOCOP1ROMONBit 0EEON0000000000000000UU11UU(L)UU(L)1UUUUUUUOPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATACONFIG — System Configuration (MC68HC811E2 only)Bit 7RESETS:S. chipBootExpTest$103F6EE35EE24EE13EE02NOSEC1NOCOPBit 0—EEON11UU11UU11UU11UUUU11UU(L)UU(L)111111U0U indicates a previously programmed bit. U(L) indicates that the bit resets to the logiclevel held in the latch prior to reset, but the function of COP is controlled by DISR bitin TEST1 register.EE[3:0] — EEPROM MappingEE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to beremapped to any 4-Kbyte boundary. Refer to Table 4-4.4Table 4-4 EEPROM MappingEE[3:0]EEPROM Location0000$0800 – $0FFF0001$1800 – $1FFF0010$2800 – $2FFF0011$3800 – $3FFF0100$4800 – $4FFF0101$5800 – $5FFF0110$6800 – $6FFF0111$7800 – $7FFF1000$8800 – $8FFF1001$9800 – $8FFF1010$A800 – $AFFF1011$B800 – $BFFF1100$C800 – $CFFF1101$D800 – $DFFF1110$E800 – $EFFF1111$F800 – $FFFFNOSEC — Security DisableNOSEC is invalid unless the security mask option is specified before the MCU is manufactured.
If the security mask option is omitted NOSEC always reads one. The enhanced security feature is available in the MC68S711E9 MCU. The enhancement tothe standard security feature protects the EPROM as well as RAM and EEPROM.0 = Security enabled1 = Security disabledNOCOP — COP System DisableRefer to SECTION 5 RESETS AND INTERRUPTS.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-13ROMON — ROM/EPROM/OTPROM EnableWhen this bit is zero, the ROM or EPROM is disabled and that memory space becomes externally addressed. In single-chip mode, ROMON is forced to one to enableROM/EPROM regardless of the state of the ROMON bit.0 = ROM disabled from the memory map1 = ROM present in the memory mapEEON — EEPROM EnableWhen this bit is zero, the EEPROM is disabled and that memory space becomes externally addressed.0 = EEPROM removed from the memory map1 = EEPROM present in the memory map44.2.2.2 INIT RegisterThe internal registers used to control the operation of the MCU can be relocated on 4Kbyte boundaries within the memory space with the use of INIT.
This 8-bit special-purpose register can change the default locations of the RAM and control registers withinthe MCU memory map. It can be written only once within the first 64 E-clock cyclesafter a reset in normal modes, and then it becomes a read-only register.INIT — RAM and I/O Mapping RegisterRESET:Bit 7RAM306RAM205RAM10$103D4RAM003REG302REG201REG10Bit 0REG01RAM[3:0] — RAM Map PositionThese four bits, which specify the upper hexadecimal digit of the RAM address, controlposition of RAM in the memory map. RAM can be positioned at the beginning of any4-Kbyte page in the memory map.
It is initialized to address $0000 out of reset. Referto Table 4-5.REG[3:0] — 64-Byte Register Block PositionThese four bits specify the upper hexadecimal digit of the address for the 64-byte blockof internal registers. The register block, positioned at the beginning of any 4-Kbytepage in the memory map, is initialized to address $1000 out of reset. Refer to Table4-6.MOTOROLA4-14OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATATable 4-5 RAM MappingTable 4-6 Register MappingRAM[3:0]AddressREG[3:0]Address0000$0000 – $0xFF0000$0000 – $003F0001$1000 – $1xFF0001$1000 – $103F0010$2000 – $2xFF0010$2000 – $203F0011$3000 – $3xFF0011$3000 – $303F0100$4000 – $4xFF0100$4000 – $403F0101$5000 – $5xFF0101$5000 – $503F0110$6000 – $6xFF0110$6000 – $603F0111$7000 – $7xFF0111$7000 – $703F1000$8000 – $8xFF1000$8000 – $803F1001$9000 – $9xFF1001$9000 – $903F1010$A000 – $AxFF1010$A000 – $A03F1011$B000 – $BxFF1011$B000 – $B03F1100$C000 – $CxFF1100$C000 – $C03F1101$D000 – $DxFF1101$D000 – $D03F1110$E000 – $ExFF1110$E000 – $E03F1111$F000 – $FxFF1111$F000 – $F03F44.2.2.3 OPTION RegisterThe 8-bit special-purpose OPTION register sets internal system configuration optionsduring initialization.
The time protected control bits, IRQE, DLY, and CR[1:0] can bewritten only once after a reset and then become read-only. This minimizes the possibility of any accidental changes to the system configuration.OPTION — System Configuration OptionsRESET:$1039Bit 7ADPU6CSEL5IRQE143CME2—1Bit 0DLY1CR110001000CR010NOTES:1. Can be written only once in first 64 cycles out of reset in normal modes, or at any time during specialmodes.ADPU — Analog-to-Digital Converter Power-UpRefer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.CSEL — Clock SelectSelects alternate clock source for on-chip EEPROM charge pump. Refer to 4.4.1 EEPROM Programming for more information on EEPROM use.
CSEL also selects theclock source for the A/D converter, a function discussed in SECTION 10 ANALOGTO-DIGITAL CONVERTER.IRQE — Configure IRQ for Edge-Sensitive Only OperationRefer to SECTION 5 RESETS AND INTERRUPTS.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-15DLY — Enable Oscillator Startup Delay0 = The oscillator startup delay coming out of STOP is bypassed and the MCUresumes processing within about four bus cycles.1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started up from the STOP power-saving mode. This delay allows the crystal oscillator to stabilize.CME — Clock Monitor EnableRefer to SECTION 5 RESETS AND INTERRUPTS.Bit 2 — Not implementedAlways reads zeroCR[1:0] — COP Timer Rate Select BitsThe internal E clock is divided by 215 before it enters the COP watchdog system.These control bits determine a scaling factor for the watchdog timer. Refer to SECTION 5 RESETS AND INTERRUPTS.44.3 EPROM/OTPROMCertain devices in the M68HC11 E series include on-chip EPROM/OTPROM.
TheMC68HC711E9 devices contain 12 Kbytes of on-chip EPROM (OTPROM in non-windowed package). The MC68HC711E20 has 20 Kbytes of EPROM (OTPROM in nonwindowed package).Using the on-chip EPROM/OTPROM programming feature requires an external 12volt nominal power supply (VPPE). Normal programming is accomplished using theEPROM/OTPROM programming register (PPROG). PPROG is the combinedEPROM/OTPROM and EEPROM programming register on all devices with EPROM/OTPROM except the MC68HC711E20. For the MC68HC711E20, there is a separateregister for EPROM/OTPROM programming called the EPROG register. There aretwo possible methods of programming and verifying EPROM.4.3.1 Programming an Individual EPROM AddressIn this method, the MCU programs its own EPROM by controlling the PPROG register(EPROG in MC68HC711E20).
Use the following procedure to program the EPROMthrough the MCU with the ROMON bit set in the CONFIG register. The 12 volt nominalprogramming voltage must be present on the XIRQ/VPPE pin. Any operating modecan be used. The first example applies to all devices with EPROM/OTPROM exceptMC68HC711E20. The second example applies to the MC68HC711E20 only.MOTOROLA4-16OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATAEPROGLDABSTAB#$20$103BSTAALDABSTAB$0,X#$21$103BJSRCLRDLYEP$103BSet ELAT bit in (EPGM=0) to enable EPROMlatches.Store data to EPROM addressSet EPGM bit with ELAT=1 to enable EPROMprogramming voltageDelay 2–4 msTurn off programming voltage and set to READ modeThe following example applies only to MC68HC711E20.EPROGLDABSTABSTAALDABSTAB#$20$1036$0,X#$21$1036JSRCLRDLYEP$1036Set ELAT bit (EPGM=0) to enable EPROM latches.Store data to EPROM addressSet EPGM bit with ELAT=1 to enable EPROMprogramming voltageDelay 2–4 msTurn off programming voltage and set to READ modeIf the MCU is operating with programming voltage present on the XIRQ/VPPE pin, theIRQ/CE pin must be pulled to a high level before the address and data are changed toprogram the next location.4.3.2 Programming EPROM with Downloaded DataWhen using this method, the EPROM is programmed by software while in the specialtest or bootstrap modes.
User-developed software can be uploaded through the SCI,or a ROM-resident EPROM programming utility can be used.The 12 volt nominal programming voltage must be present on the XIRQ/VPPE pin. To use the resident utility,bootload a three-byte program consisting of a single jump instruction to $BF00. $BF00is the starting address of a resident EPROM programming utility. The utility programsets the X and Y index registers to default values, then receives programming datafrom an external host and puts it in EPROM.
The value in IX determines programmingdelay time. The value in IY is a pointer to the first address in EPROM to be programmed (default = $D000).When the utility program is ready to receive programming data, it sends the host the$FF character. Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting with the first location in the EPROM array. After the lastbyte to be programmed is sent and the corresponding verification data is returned, theprogramming operation is terminated by resetting the MCU.4.3.3 EPROM Programming Control RegisterThe PPROG register enables the EPROM programming voltage and controls thelatching of data to be programmed.
For MC68HC711E9, PPROG is also the EEPROMprogramming control register. In the MC68HC711E20 EPROM programming is controlled by the EPROG register and EEPROM programming is controlled by thePPROG register.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-174PPROG — EPROM and EEPROM Programming ControlRESET:Bit 7ODD06EVEN05ELAT104BYTE03ROW0$103B2ERASE01EELAT0Bit 0EPGM0NOTES:1.
MC68HC711E9 only.ODD — Program Odd Rows in Half of EEPROM (Test)Refer to 4.4 EEPROM.EVEN — Program Even Rows in Half of EEPROM (Test)Refer to 4.4 EEPROM.4ELAT — EPROM/OTPROM Latch ControlWhen ELAT = 1, writes to EPROM cause address and data to be latched and theEPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be writtenany time except when EPGM = 1; then the write to ELAT is disabled. For theMC68HC711E9, EPGM enables the high voltage necessary for both EEPROM andEPROM/OTPROM programming.
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