Микроконтроллер Motorola 68HC11 (1086181), страница 6
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A high on this pin indicates that a read cycle is in progress.R/W stays low during consecutive data bus write cycles, such as a double-byte store.It is possible for data to be driven out port C, if internal read visibility is enabled and anM68HC11 E SERIESTECHNICAL DATAPIN DESCRIPTIONSMOTOROLA2-92internal address is read, even though R/W is in a high-impedance state. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information aboutIRVNE.2.11 Port SignalsPort pins have different functions in different operating modes. Pin functions for portsA, D, and E are independent of operating modes.
Ports B and C, however, are affectedby operating mode. Port B provides eight general-purpose output signals in single-chipoperating modes. When the microcontroller is in expanded multiplexed operatingmode, port B pins are the eight high-order address lines. Port C provides eight general-purpose input/output signals when the MCU is in the single-chip operating mode.When the microcontroller is in the expanded multiplexed operating mode, port C pinsare a multiplexed address/data bus.
Refer to Table 2-1 for details about functions ofthe 40 port signals within different operating modes. Terminate unused inputs and I/Opins configured as inputs high or low.2Table 2-1 Port Signal FunctionsPort/BitPA0PA1PA2PA3PA4PA5PA6PA7PB0PB1PB2PB3PB4PB5PB6PB7PC0PC1PC2PC3PC4PC5PC6PC7PD0PD1PD2PD3PD4MOTOROLA2-10Single-Chip andBootstrap ModesExpanded andTest ModesPA0/IC3PA1/IC2PA2/IC1PA3/OC5/IC4/OC1PA4/OC4/OC1PA5/OC3/OC1PA6/OC2/OC1PA7/PAI/OC1PB0PB1PB2PB3PB4PB5PB6PB7PC0PC1PC2PC3PC4PC5PC6PC7ADDR8ADDR9ADDR10ADDR11ADDR12ADDR13ADDR14ADDR15ADDR0/DATA0ADDR1/DATA1ADDR2/DATA2ADDR3/DATA3ADDR4/DATA4ADDR5/DATA5ADDR6/DATA6ADDR7/DATA7PD0/RxDPD1/TxDPD2/MISOPD3/MOSIPD4/SCKPIN DESCRIPTIONSM68HC11 E SERIESTECHNICAL DATATable 2-1 Port Signal FunctionsPort/BitPD5——PE0PE1PE2PE3PE4PE5PE6PE7Single-Chip andBootstrap ModesExpanded andTest ModesPD5/SSSTRASTRBASR/WPE0/AN0PE1/AN1PE3/AN2PE3/AN3PE4/AN4PE5/AN5PE6/AN6PE7/AN72.11.1 Port AIn all operating modes, port A can be configured for three timer input capture (IC) functions and four timer output compare (OC) functions.
An additional pin can be configured as either the fourth IC or the fifth OC. Any port A pin that is not currently beingused for a timer function can be used as either a general-purpose input or output line.Only port A pins PA7 and PA3 have an associated data direction control bit that allowsthe pin to be selectively configured as input or output. Bits DDRA7 and DDRA3 locatedin PACTL register control data direction for PA7 and PA3, respectively. All other portA pins are fixed as either input or output.PA7 can function as general-purpose I/O or as timer output compare for OC1. PA7 isalso the input to the pulse accumulator, even while functioning as a general-purposeI/O or an OC1 output.PA[6:4] serve as either general-purpose outputs, timer input captures or timer outputcompare 2–4.
In addition, PA[6:4] can be controlled by OC1.PA3 can be a general-purpose I/O pin or a timer IC/OC pin. Timer functions associatedwith this pin include OC1 and IC4/OC5. IC4/OC5 is software selectable as either afourth input capture or a fifth output compare. PA3 can also be configured to allow OC1edges to trigger IC4 captures.PA[2:0] serve as general-purpose inputs or as IC[1:3].PORTA can be read at any time. Reads of pins configured as inputs return the logiclevel present on the pin.
Pins configured as outputs return the logic level present at thepin driver input. If written, PORTA stores the data in an internal latch, bits 7 and 3. Itdrives the pins only if they are configured as outputs. Writes to PORTA do not changethe pin state when pins are configured for timer input captures or output compares. Refer to SECTION 6 PARALLEL INPUT/OUTPUT.2.11.2 Port BDuring single-chip operating modes, all port B pins are general-purpose output pins.During MCU reads of this port, the level sensed at the input side of the port B outputM68HC11 E SERIESTECHNICAL DATAPIN DESCRIPTIONSMOTOROLA2-112drivers is read. Port B can also be used in simple strobed output mode. In this mode,an output pulse appears at the STRB signal each time data is written to port B.In expanded multiplexed operating modes, all of the port B pins act as high order address output signals.
During each MCU cycle, bits [15:8] of the address bus are outputon the PB[7:0] pins. The PORTB register is treated as an external address in expanded modes.2.11.3 Port CWhile in single-chip operating modes, all port C pins are general-purpose input/outputpins. Port C inputs can be latched into an alternate PORTCL register by providing aninput transition to the STRA signal.
Port C can also be used in full handshake modesof parallel I/O where the STRA input and STRB output act as handshake control lines.2When in expanded multiplexed modes, all port C pins are configured as multiplexedaddress/data signals. During the address portion of each MCU cycle, bits [7:0] of theaddress are output on the PC[7:0] pins. During the data portion of each MCU cycle (Ehigh), PC[7:0] are bidirectional data signals, DATA[7:0]. The direction of data at theport C pins is indicated by the R/W signal.The CWOM control bit in the PIOC register disables the port C P-channel output driver.CWOM simultaneously affects all eight bits of port C.
Because the N-channel driver isnot affected by CWOM, setting CWOM causes port C to become an open-drain-typeoutput port suitable for wired-OR operation. In wired-OR mode, when a port C bit is atlogic level zero, it is driven low by the N-channel driver.
When a port C bit is at logiclevel one, the associated pin has high-impedance, as neither the N- nor the P-channeldevices are active. It is customary to have an external pull-up resistor on lines that aredriven by open-drain devices. Port C can only be configured for wired-OR operationwhen the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL INPUT/OUTPUT for additional information about port C functions.2.11.4 Port DPins PD[5:0] can be used for general-purpose I/O signals. These pins alternatelyserve as the serial communication interface (SCI) and serial peripheral interface (SPI)signals when those subsystems are enabled.Pin PD0 is the receive data input (RxD) signal for the SCI.Pin PD1 is the transmit data output (TxD) signal for the SCI.Pins PD[5:2] are dedicated to the serial peripheral interface (SPI).
PD2 is the masterin slave out (MISO) signal. PD3 is the master out slave in (MOSI) signal. PD4 is theserial clock (SCK) signal and PD5 is the slave select (SS) input.2.11.5 Port EUse port E for general-purpose or analog-to-digital (A/D) inputs. If high accuracy is required for A/D conversions, avoid reading port E during sampling, as small disturbances can reduce the accuracy of that result.MOTOROLA2-12PIN DESCRIPTIONSM68HC11 E SERIESTECHNICAL DATASECTION 3 CENTRAL PROCESSING UNITThis section presents information on M68HC11 central processing unit (CPU) architecture, data types, addressing modes, the instruction set, and special operationssuch as subroutine calls and interrupts.The CPU is designed to treat all peripheral, I/O, and memory locations identically asaddresses in the 64 Kbyte memory map. This is referred to as memory-mapped I/O.There are no special instructions for I/O that are separate from those used for memory.This architecture also allows accessing an operand from an external memory locationwith no execution-time penalty.3.1 CPU RegistersM68HC11 CPU registers are an integral part of the CPU and are not addressed as ifthey were memory locations.
The seven registers, discussed in the following paragraphs, are shown in Figure 3-1.715A07B00D8-BIT ACCUMULATORS A & BOR 16-BIT DOUBLE ACCUMULATOR DIXINDEX REGISTER XIYINDEX REGISTER YSPSTACK POINTERPCPROGRAM COUNTER7S0XHINZVCCONDITION CODESCARRY/BORROW FROM MSBOVERFLOWZERONEGATIVEI-INTERRUPT MASKHALF CARRY (FROM BIT 3)X-INTERRUPT MASKSTOP DISABLEHC11 PROG MODELFigure 3-1 Programming ModelM68HC11 E SERIESTECHNICAL DATACENTRAL PROCESSING UNITMOTOROLA3-133.1.1 Accumulators A, B, and DAccumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations.
For some instructions, these twoaccumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators A or B interchangeably, thefollowing exceptions apply:The ABX and ABY instructions add the contents of 8-bit accumulator B to the contentsof 16-bit register X or Y, but there are no equivalent instructions that use A instead of B.The TAP and TPA instructions transfer data from accumulator A to the condition coderegister, or from the condition code register to accumulator A, however, there are noequivalent instructions that use B rather than A.The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations, but there is no equivalent BCD instruction to adjustaccumulator B.3The add, subtract, and compare instructions associated with both A and B (ABA, SBA,and CBA) only operate in one direction, making it important to plan ahead to ensurethat the correct operand is in the correct accumulator.3.1.2 Index Register X (IX)The IX register provides a 16-bit indexing value that can be added to the 8-bit offsetprovided in an instruction to create an effective address.
The IX register can also beused as a counter or as a temporary storage register.3.1.3 Index Register Y (IY)The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most instructions using the IY register require an extra byte of machinecode and an extra cycle of execution time because of the way the opcode map is implemented. Refer to 3.3 Opcodes and Operands for further information.3.1.4 Stack Pointer (SP)The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address space and can be any size up to the amount of memory availablein the system.
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