Микроконтроллер Motorola 68HC11 (1086181), страница 5
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VDD is the power supply, VSS isground. The MCU operates from a single 5-volt (nominal) power supply. Low-voltagedevices in the E series operate at either 3.0 – 5.5 volts or 2.7 – 5.5 volts. Very fast signal transitions occur on the MCU pins. The short rise and fall times place high, shortduration current demands on the power supply. To prevent noise problems, providegood power supply bypassing at the MCU.
Also, use bypass capacitors that have goodhigh-frequency characteristics and situate them as close to the MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded.2.2 RESETA bidirectional control signal, RESET, acts as an input to initialize the MCU to a knownstart-up state. It also acts as an open-drain output to indicate that an internal failurehas been detected in either the clock monitor or COP watchdog circuit. The CPU distinguishes between internal and external reset conditions by sensing whether the resetpin rises to a logic one in less than two E-clock cycles after a reset has occurred.
DoM68HC11 E SERIESTECHNICAL DATAPIN DESCRIPTIONSMOTOROLA2-5not connect an external resistor capacitor (RC) power-up delay circuit to the reset pinof M68HC11 devices because the circuit charge time constant can cause the deviceto misinterpret the type of reset that occurred. Refer to SECTION 5 RESETS AND INTERRUPTS for further information.VDDVDD24.7 kΩINRESETMC34(0/1)641TO RESETOF M68HC11GND3EXT RESET CIRCUITFigure 2-6 External Reset Circuit2VDDVDDINRESETMC34064GNDVDDTO RESETOF M68HC114.7 kΩMANUALRESET SWITCH4.7 kΩ1.0 µFINRESETMC34164GNDOPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCHEXT RESET CIRCUIT W/DELAYFigure 2-7 External Reset Circuit with Delay2.3 Crystal Driver and External Clock Input (XTAL, EXTAL)These two pins provide the interface for either a crystal or a CMOS compatible clockto control the internal clock generator circuitry.
The frequency applied to these pins isfour times higher than the desired E-clock rate.MOTOROLA2-6PIN DESCRIPTIONSM68HC11 E SERIESTECHNICAL DATAThe XTAL pin is normally left unterminated when an external CMOS compatible clockinput is connected to the EXTAL pin. However, a 10 kΩ to 100 kΩ load resistor connected from XTAL to ground can be used to reduce RFI noise emission. The XTALoutput is normally intended to drive only a crystal.
The XTAL output can be bufferedwith a high-impedance buffer, or it can be used to drive the EXTAL input of anotherM68HC11 MCU.In all cases, use caution around the oscillator pins. Load capacitances shown in theoscillator circuits include all stray layout capacitances. Refer to Figure 2-8, Figure 29, and Figure 2-10.25 pF *EXTAL10 MΩMCU4xECRYSTAL25 pF *XTAL2* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.COMMON XTAL CONNFigure 2-8 Common Crystal Connections4xECMOS-COMPATIBLEEXTERNAL OSCILLATOREXTALMCUXTALNCEXT EXTAL CONNFigure 2-9 External Oscillator ConnectionsM68HC11 E SERIESTECHNICAL DATAPIN DESCRIPTIONSMOTOROLA2-725 pF *220 ΩEXTALEXTAL10 MΩFIRSTMCUSECONDMCU4xECRYSTAL25 pF *XTAL* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.NCXTALDUAL-MCU XTAL CONNFigure 2-10 One Crystal Driving Two MCUs22.4 E-Clock Output (E)E is the output connection for the internally generated E clock.
The signal from E isused as a timing reference. The frequency of the E-clock output is one fourth that ofthe input frequency at the XTAL and EXTAL pins. When E-clock output is low, an internal process is taking place. When it is high, data is being accessed. All clocks, including the E clock, are halted when the MCU is in STOP mode. To reduce RFIemissions, the E-clock output of most E-series devices can be disabled while operating in single-chip modes. The E clock signal is always enabled on the MC68HC811E2.2.5 Interrupt Request (IRQ)The IRQ input provides a means of applying asynchronous interrupt requests to theMCU. Either negative edge-sensitive triggering or level-sensitive triggering is programselectable (OPTION register).
IRQ is always configured to level-sensitive triggering atreset. When using IRQ in a level-sensitive wired-OR configuration, connect an external pull-up resistor, typically 4.7 kΩ, to VDD.2.6 Non-Maskable Interrupt (XIRQ/VPPE)The XIRQ input provides a means of requesting a non-maskable interrupt after resetinitialization. During reset, the X bit in the condition code register (CCR) is set and anyinterrupt is masked until MCU software enables it. Because the XIRQ input is levelsensitive, it can be connected to a multiple-source wired-OR network with an externalpull-up resistor to VDD. XIRQ is often used as a power loss detect interrupt.Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sensitive operation if there is more than one source of IRQ interrupt),each source must drive the interrupt input with an open-drain type of driver to avoidcontention between outputs.
There should be a single pull-up resistor near the MCUinterrupt input pin (typically 4.7 kΩ). There must also be an interlock mechanism ateach interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If one or more interrupt sources arestill pending after the MCU services a request, the interrupt line will still be held lowand the MCU will be interrupted again as soon as the interrupt mask bit in the MCU iscleared (normally upon return from an interrupt).
Refer to SECTION 5 RESETS ANDMOTOROLA2-8PIN DESCRIPTIONSM68HC11 E SERIESTECHNICAL DATAINTERRUPTS.VPPE is the input for the 12 volt nominal programming voltage required for EPROM/OTPROM programming. On devices without EPROM/OTPROM this pin is only XIRQinput.2.7 MODA and MODB (MODA/LIR and MODB/VSTBY)During reset, MODA and MODB select one of the four operating modes. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.After the operating mode has been selected, the load instruction register (LIR) pin provides an open-drain output to indicate that execution of an instruction has begun.
Aseries of E-clock cycles occurs during execution of each instruction. The LIR signalgoes low during the first E-clock cycle of each instruction (opcode fetch). This outputis provided for assistance in program debugging.The VSTBY pin is used to input RAM standby power.
When the voltage on this pin ismore than one MOS threshold (about 0.7 volts) above the VDD voltage, the internalRAM and part of the reset logic are powered from this signal rather than the VDD input.This allows RAM contents to be retained without VDD power applied to the MCU. Reset must be driven low before VDD is removed and must remain low until VDD hasbeen restored to a valid level.2.8 VRL and VRHThese two inputs provide the reference voltages for the analog-to-digital converter circuitry.
VRL is the low reference, typically 0 Vdc. VRH is the high reference. For properA/D converter operation, VRH should be at least 3 Vdc greater than VRL, and both VRLand VRH should be between VSS and VDD.2.9 STRA/ASThis pin performs either of two separate functions, depending on the operating mode.In single-chip mode, STRA performs an input handshake (strobe input) function. In theexpanded multiplexed mode, AS provides an address strobe function.
AS can be usedto demultiplex the address and data signals at port C. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.2.10 STRB/R/WThe strobe B and read/write pin acts as either an output strobe, or as a data bus direction indicator, depending on the operating mode. In single-chip operating mode, STRBacts as a programmable strobe for handshake with other parallel devices. Refer toSECTION 6 PARALLEL INPUT/OUTPUT for further information.In expanded multiplexed operating mode, R/W is used to indicate the direction oftransfers on the external data bus. A low on the R/W pin indicates data is being writtento the external data bus.
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