Микроконтроллер Motorola 68HC11 (1086181), страница 18
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This addressing scheme can take any form as long as all transmitting and receiving devices are programmed to understand the same scheme. Because theaddressing information is usually the first frame(s) in a message, receivers that are notpart of the current task do not become burdened with the entire set of addressingframes.
All receivers are awake (RWU = 0) when each message begins. As soon asa receiver determines that the message is not intended for it, software sets the RWUbit (RWU = 1), which inhibits further flag setting until the RxD line goes idle at the endof the message. As soon as an idle line is detected by receiver logic, hardware automatically clears the RWU bit so that the first frame of the next message can be received. This type of receiver wakeup requires a minimum of one idle-line frame timebetween messages, and no idle time between frames in a message.7.4.2 Address-Mark WakeupThe serial characters in this type of wakeup consist of seven (eight if M = 1) informationbits and an MSB, which indicates an address character (when set to one, or mark).The first character of each message is an addressing character (MSB = 1).
All receivers in the system evaluate this character to determine if the remainder of the messageis directed toward this particular receiver. As soon as a receiver determines that amessage is not intended for it, the receiver activates the RWU function by using a software write to set the RWU bit. Because setting RWU inhibits receiver-related flags,there is no further software overhead for the rest of this message.When the next message begins, its first character has its MSB set, which automaticallyclears the RWU bit and enables normal character reception. The first character whoseMSB is set is also the first character to be received after wakeup because RWU getscleared before the stop bit for that frame is serially received.
This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but there is aloss of efficiency because of the extra bit time for each character (address bit) requiredfor all characters.M68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-577.5 SCI Error DetectionThree error conditions, SCDR overrun, received bit noise, and framing can occur during generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial communications status register (SCSR) indicate if one of these error conditions exists.The overrun error (OR) bit is set when the next byte is ready to be transferred from thereceive shift register to the SCDR and the SCDR is already full (RDRF bit is set).
Whenan overrun error occurs, the data that caused the overrun is lost and the data that wasalready in SCDR is not disturbed. The OR is cleared when the SCSR is read (with ORset), followed by a read of the SCDR.The noise flag (NF) bit is set if there is noise on any of the received bits, including thestart and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is clearedwhen the SCSR is read (with FE equal to one) followed by a read of the SCDR.7When no stop bit is detected in the received data character, the framing error (FE) bitis set.
FE is set at the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor only recognizes the overrun error. The framingerror flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit iscleared when the SCSR is read (with FE equal to one) followed by a read of the SCDR.7.6 SCI RegistersThere are five addressable registers associated with the SCI.
SCCR1, SCCR2, andBAUD are control registers. SCDR is the SCI data register and SCSR is the SCI statusregister. The SCI registers are the same for all M68HC11 E-series devices with oneexception. The SCI system for MC68HC(7)11E20 contains an extra bit in the BAUDregister that provides a greater selection of baud prescaler rates. Refer to the BAUDregister description as well as the block diagrams for the baud rate prescalers.7.6.1 Serial Communications Data RegisterSCDR is a parallel register that performs two functions. It is the receive data registerwhen it is read, and the transmit data register when it is written.
Reads access the receive data buffer and writes access the transmit data buffer. Receive and transmit aredouble buffered.SCDR — SCI Data RegisterRESET:Bit 7R7/T7I6R6/T6I$102F5R5/T5I4R4/T4I3R3/T3I2R2/T2I1R1/T1IBit 0R0/T0I7.6.2 Serial Communications Control Register 1The SCCR1 register provides the control bits that determine word length and selectthe method used for the wakeup feature.MOTOROLA7-6SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATASCCR1 — SCI Control Register 1RESET:Bit 7R8I6T8I$102C5—04M03WAKE02—01—0Bit 0—0R8 — Receive Data Bit 8If M bit is set, R8 stores the ninth bit in the receive data character.T8 — Transmit Data Bit 8If M bit is set, T8 stores the ninth bit in the transmit data character.Bit 5 — Not implementedAlways reads zeroM — Mode (Select Character Format)0 = Start bit, 8 data bits, 1 stop bit1 = Start bit, 9 data bits, 1 stop bit7WAKE — Wakeup by Address Mark/Idle0 = Wakeup by IDLE line recognition1 = Wakeup by address mark (most significant data bit set)Bits [2:0] — Not implementedAlways read zero7.6.3 Serial Communications Control Register 2The SCCR2 register provides the control bits that enable or disable individual SCIfunctions.SCCR2 — SCI Control Register 2RESET:Bit 7TIE06TCIE0$102D5RIE04ILIE03TE02RE01RWU0Bit 0SBK0TIE — Transmit Interrupt Enable0 = TDRE interrupts disabled1 = SCI interrupt requested when TDRE status flag is setTCIE — Transmit Complete Interrupt Enable0 = TC interrupts disabled1 = SCI interrupt requested when TC status flag is setRIE — Receiver Interrupt Enable0 = RDRF and OR interrupts disabled1 = SCI interrupt requested when RDRF flag or the OR status flag is setM68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-7ILIE — Idle-Line Interrupt Enable0 = IDLE interrupts disabled1 = SCI interrupt requested when IDLE status flag is setTE — Transmitter EnableWhen TE goes from zero to one, one unit of idle character time (logic one) is queuedas a preamble.0 = Transmitter disabled1 = Transmitter enabledRE — Receiver Enable0 = Receiver disabled1 = Receiver enabledRWU — Receiver Wakeup Control0 = Normal SCI receiver1 = Wakeup enabled and receiver interrupts inhibited7SBK — Send BreakAt least one character time of break is queued and sent each time SBK is written toone.
As long as the SBK bit is set, break characters are queued and sent. More thanone break may be sent if the transmitter is idle at the time the SBK bit is toggled onand off, as the baud rate clock edge could occur between writing the one and writingthe zero to SBK.0 = Break generator off1 = Break codes generated7.6.4 Serial Communication Status RegisterThe SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt.SCSR — SCI Status RegisterRESET:Bit 7TDRE16TC1$102E5RDRF04IDLE03OR02NF01FE0Bit 0—0TDRE — Transmit Data Register Empty FlagThis flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR withTDRE set and then writing to SCDR.0 = SCDR busy1 = SCDR emptyTC — Transmit Complete FlagThis flag is set when the transmitter is idle (no data, preamble, or break transmissionin progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR.0 = Transmitter busy1 = Transmitter idleMOTOROLA7-8SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATARDRF — Receive Data Register Full FlagThis flag is set if a received character is ready to be read from SCDR.
Clear the RDRFflag by reading SCSR with RDRF set and then reading SCDR.0 = SCDR empty1 = SCDR fullIDLE — Idle Line Detected FlagThis flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxDline has been active and becomes idle again. The IDLE flag is inhibited when RWU =1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR.0 = RxD line is active1 = RxD line is idleOR — Overrun Error FlagOR is set if a new character is received before a previously received character is readfrom SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR.0 = No overrun1 = Overrun detectedNF — Noise Error FlagNF is set if majority sample logic detects anything other than a unanimous decision.Clear NF by reading SCSR with NF set and then reading SCDR.0 = Unanimous decision1 = Noise detectedFE — Framing ErrorFE is set when a zero is detected where a stop bit was expected.
Clear the FE flag byreading SCSR with FE set and then reading SCDR.0 = Stop bit detected1 = Zero detectedBit 0 — Not implementedAlways reads zero.7.6.5 Baud Rate RegisterUse this register to select different baud rates for the SCI system. The SCP[1:0](SCP[2:0] in MC68HC(7)11E20) bits function as a prescaler for the SCR[2:0] bits. Together, these five bits provide multiple baud rate combinations for a given crystal frequency. Normally, this register is written once during initialization.
The prescaler is setto its fastest rate by default out of reset, and can be changed at any time. Refer to Table 7-1 and Table 7-2 for normal baud rate selections.BAUD — Baud RateRESET:Bit 7TCLR0M68HC11 E SERIESTECHNICAL DATA$102B6SCP205SCP104SCP003RCKB02SCR2USERIAL COMMUNICATIONS INTERFACE1SCR1UBit 0SCR0UMOTOROLA7-97TCLR — Clear Baud Rate Counters (Test)SCP[2:0] — SCI Baud Rate Prescaler SelectsNote that SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] mustequal zeros.
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