Микроконтроллер Motorola 68HC11 (1086181), страница 24
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The PACNT is readable even if PAI is not active in gated time accumulation mode. The counter is not affected by reset and can be read orwritten at any time. Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles.M68HC11 E SERIESTECHNICAL DATATIMING SYSTEMMOTOROLA9-179PACNT — Pulse Accumulator CountBit 7Bit 76655$102744332211Bit 0Bit 09.6.3 Pulse Accumulator Status and Interrupt BitsThe pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF, are locatedwithin timer registers TMSK2 and TFLG2.TMSK2 — Timer Interrupt Mask 2 RegisterRESET:9Bit 7TOI06RTII05PAOVI04PAII0$10243—02—01PR10Bit 0PR00TFLG2 — Timer Interrupt Flag 2 RegisterRESET:Bit 7TOF06RTIF05PAOVF0$10254PAIF03—02—01—0Bit 0—0PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow FlagThe PAOVF status bit is set each time the pulse accumulator count rolls over from $FFto $00. To clear this status bit, write a one in the corresponding data bit position (bit 5)of the TFLG2 register.
The PAOVI control bit allows configuring the pulse accumulatoroverflow for polled or interrupt-driven operation and does not affect the state ofPAOVF. When PAOVI is zero, pulse accumulator overflow interrupts are inhibited, andthe system operates in a polled mode, which requires that PAOVF be polled by usersoftware to determine when an overflow has occurred. When the PAOVI control bit isset, a hardware interrupt request is generated each time PAOVF is set. Before leavingthe interrupt service routine, software must clear PAOVF by writing to the TFLG2 register.PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and FlagThe PAIF status bit is automatically set each time a selected edge is detected at thePA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a one in thecorresponding data bit position (bit 4).
The PAII control bit allows configuring the pulseaccumulator input edge detect for polled or interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII is zero, pulse accumulator input interrupts are inhibited, and the system operates in a polled mode. In this mode, the PAIFbit must be polled by user software to determine when an edge has occurred. Whenthe PAII control bit is set, a hardware interrupt request is generated each time PAIF isset. Before leaving the interrupt service routine, software must clear PAIF by writing tothe TFLG2 register.MOTOROLA9-18TIMING SYSTEMM68HC11 E SERIESTECHNICAL DATASECTION 10 ANALOG-TO-DIGITAL CONVERTERThe analog-to-digital (A/D) system, a successive approximation converter, uses an allcapacitive charge redistribution technique to convert analog signals to digital values.10.1 OverviewThe A/D system is an 8-channel, 8-bit, multiplexed-input converter.
The converterdoes not require external sample and hold circuits because of the type of charge redistribution technique used. A/D converter timing can be synchronized to the systemE clock, or to an internal resistor capacitor (RC) oscillator. The A/D converter systemconsists of four functional blocks: multiplexer, analog converter, digital control, and result storage. Refer to Figure 10-1.10.1.1 MultiplexerThe multiplexer selects one of 16 inputs for conversion. Input selection is controlled bythe value of bits CD:CA in the ADCTL register.
The eight port E pins are fixed- directionanalog inputs to the multiplexer, and additional internal analog signal lines are routedto it.M68HC11 E SERIESTECHNICAL DATAANALOG-TO-DIGITAL CONVERTERMOTOROLA10-110PE0AN0VRH8-BIT CAPACITIVE DACWITH SAMPLE AND HOLDPE1AN1VRLPE2AN2SUCCESSIVE APPROXIMATIONREGISTER AND CONTROLPE3AN3PE4AN4RESULTANALOGMUXPE5AN5CAPE7AN7SCANMULTCDCCCBPE6AN6CCF10INTERNALDATA BUSADCTL A/D CONTROLRESULT REGISTER INTERFACEADR1 A/D RESULT 1ADR2 A/D RESULT 2ADR3 A/D RESULT 3ADR4 A/D RESULT 4EA9 A/D BLOCKFigure 10-1 A/D Converter Block DiagramPort E pins can also be used as digital inputs.
Digital reads of port E pins are not recommended during the sample portion of an A/D conversion cycle, when the gate signalto the N-channel input gate is on. Because no P-channel devices are directly connected to either input pins or reference voltage pins, voltages above VDD do not cause alatchup problem, although current should be limited according to maximum ratings.Refer to Figure 10-2, which is a functional diagram of an input pin.MOTOROLA10-2ANALOG-TO-DIGITAL CONVERTERM68HC11 E SERIESTECHNICAL DATADIFFUSION/POLYCOUPLERANALOGINPUTPIN< 2 pFINPUTPROTECTIONDEVICE+ ~20VÐ ~0.7V≤ 4 KΩ+ ~12VÐ ~0.7VDUMMY N-CHANNELOUTPUT DEVICE400 nAJUNCTIONLEAKAGE*~ 20 pFDACCAPACITANCEVRL* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.ANALOG INPUT PINFigure 10-2 Electrical Model of an A/D Input Pin (Sample Mode)10.1.2 Analog ConverterConversion of an analog input selected by the multiplexer occurs in this block.
It contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive approximation register (SAR). Each conversion is a sequence of eight comparisonoperations, beginning with the most significant bit (MSB). Each comparison determines the value of a bit in the successive approximation register.The DAC array performs two functions.
It acts as a sample and hold circuit during theentire conversion sequence, and provides comparison voltage to the comparator during each successive comparison.The result of each successive comparison is stored in the SAR. When a conversionsequence is complete, the contents of the SAR are transferred to the appropriate result register.A charge pump provides switching voltage to the gates of analog switches in the multiplexer. Charge pump output must stabilize between 7 and 8 volts within up to 100 µsbefore the converter can be used. The charge pump is enabled by the ADPU bit in theOPTION register.10.1.3 Digital ControlAll A/D converter operations are controlled by bits in register ADCTL.
In addition to selecting the analog input to be converted, ADCTL bits indicate conversion status, andcontrol whether single or continuous conversions are performed. Finally, the ADCTLbits determine whether conversions are performed on single or multiple channels.10.1.4 Result RegistersFour 8-bit registers ADR[4:1] store conversion results.
Each of these registers can beaccessed by the processor in the CPU. The conversion complete flag (CCF) indicateswhen valid data is present in the result registers. The result registers are written duringa portion of the system clock cycle when reads do not occur, so there is no conflict.M68HC11 E SERIESTECHNICAL DATAANALOG-TO-DIGITAL CONVERTERMOTOROLA10-31010.1.5 A/D Converter ClocksThe CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock or an internal RC oscillator for synchronization. When E-clock frequencyis below 750 kHz, charge leakage in the capacitor array can cause errors, and the internal oscillator should be used.
When the RC clock is used, additional errors can occur because the comparator is sensitive to the additional system clock noise.10.1.6 Conversion SequenceA/D converter operations are performed in sequences of four conversions each. Aconversion sequence can repeat continuously or stop after one iteration. The conversion complete flag (CCF) is set after the fourth conversion in a sequence to show theavailability of data in the result registers. Figure 10-3 shows the timing of a typical sequence.
Synchronization is referenced to the system E clock.SAMPLE ANALOG INPUT0CONVERT FIRSTCHANNEL, UPDATEADR132BIT 62CYCBIT 52CYCBIT 42CYCBIT 32CYCBIT 22CYCBIT 12CYCLSB2CYC2CYCENDSUCCESSIVE APPROXIMATION SEQUENCECONVERT SECONDCHANNEL, UPDATEADR264CONVERT THIRDCHANNEL, UPDATEADR396CONVERT FOURTHCHANNEL, UPDATEADR4SET CC FLAGWRITE TO ADCTL10MSB4CYCLES12 E CYCLESREPEAT SEQUENCE, SCAN = 1E CLOCK128 Ñ E CYCLESA/D CONVERSION TIMFigure 10-3 A/D Conversion Sequence10.2 A/D Converter Power-Up and Clock SelectBit 7 of the OPTION register controls A/D converter power up.
Clearing ADPU removes power from and disables the A/D converter system. Setting ADPU enables theA/D converter system. Stabilization of the analog bias voltages requires a delay of asmuch as 100 µs after turning on the A/D converter. When the A/D converter system isoperating with the MCU E clock, all switching and comparator operations are inherently synchronized to the main MCU clocks. This allows the comparator output to be sampled at relatively quiet times during MCU clock cycles. Since the internal RC oscillatoris asynchronous to the MCU clock there is more error attributable to internal systemclock noise.
A/D converter accuracy is reduced slightly while the internal RC oscillatoris being used (CSEL = 1).MOTOROLA10-4ANALOG-TO-DIGITAL CONVERTERM68HC11 E SERIESTECHNICAL DATAOPTION — System Configuration OptionsRESET:$1039Bit 7ADPU6CSEL5IRQE143CME2—1Bit 0DLY1CR110001000CR010NOTES:1. Can be written only once in first 64 cycles out of reset in normal modes, or at any time in specialmodes.ADPU — A/D Power-Up0 = A/D powered down1 = A/D powered upCSEL — Clock Select0 = A/D and EEPROM use system E clock1 = A/D and EEPROM use internal RC clockIRQE — Configure IRQ for Edge-Sensitive Only OperationRefer to SECTION 5 RESETS AND INTERRUPTS.DLY — Enable Oscillator Startup Delay0 = The oscillator startup delay coming out of STOP is bypassed and the MCUresumes processing within about four bus cycles.1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started up from the STOP power-saving mode.
This delay allows the crystal oscillator to stabilize.CME — Clock Monitor EnableRefer to SECTION 5 RESETS AND INTERRUPTS.Bit 2 — Not implementedAlways reads zero.CR[1:0] — COP Timer Rate Select BitsRefer to SECTION 5 RESETS AND INTERRUPTS and SECTION 9 TIMING SYSTEM.10.3 Conversion ProcessThe A/D conversion sequence begins one E-clock cycle after a write to the A/D control/status register, ADCTL.
The bits in ADCTL select the channel and the mode of conversion.An input voltage equal to VRL converts to $00 and an input voltage equal to VRH converts to $FF (full scale), with no overflow indication. For ratiometric conversions of thistype, the source of each analog input should use VRH as the supply voltage and bereferenced to VRL.M68HC11 E SERIESTECHNICAL DATAANALOG-TO-DIGITAL CONVERTERMOTOROLA10-51010.4 Channel AssignmentsThe multiplexer allows the A/D converter to select one of sixteen analog signals.
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