Микроконтроллер Motorola 68HC11 (1086181), страница 25
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Eightof these channels correspond to port E input lines to the MCU, four of the channels areinternal reference points or test functions, and four channels are reserved. Refer to Table 10-1.Table 10-1 Converter Channel Assignments10ChannelNumber123456789 – 1213ChannelSignalAN0AN1AN2AN3AN4AN5AN6AN7ReservedVRH1Result in ADRx ifMULT = 1ADR1ADR2ADR3ADR4ADR1ADR2ADR3ADR4—ADR114VRL1ADR215(VRH)/21ADR316Reserved1ADR4NOTES:1.
Used for factory testing10.5 Single-Channel OperationThere are two types of single-channel operation. When SCAN = 0, the first type, thesingle selected channel is converted four consecutive times. The first result is storedin A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourthconversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL register. In the second type of single-channel operation,SCAN = 1, conversions continue to be performed on the selected channel with the fifthconversion being stored in register ADR1 (overwriting the first conversion result), thesixth conversion overwriting ADR2, and so on.10.6 Multiple-Channel OperationThere are two types of multiple-channel operation. When SCAN = 0, the first type, aselected group of four channels is converted one time each.
The first result is storedin A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourthconversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL register. In the second type of multiple-channel operation, SCAN = 1, conversions continue to be performed on the selected group ofchannels with the fifth conversion being stored in register ADR1 (replacing the earlierconversion result for the first channel in the group), the sixth conversion overwritingADR2, and so on.MOTOROLA10-6ANALOG-TO-DIGITAL CONVERTERM68HC11 E SERIESTECHNICAL DATA10.7 Operation in STOP and WAIT ModesIf a conversion sequence is in progress when either the STOP or WAIT mode is entered, the conversion of the current channel is suspended. When the MCU resumesnormal operation, that channel is resampled and the conversion sequence is resumed.As the MCU exits the WAIT mode, the A/D circuits are stable and valid results can beobtained on the first conversion.
However, in STOP mode, all analog bias currents aredisabled and it is necessary to allow a stabilization period when leaving the STOPmode. If the STOP mode is exited with a delay (DLY = 1), there is enough time forthese circuits to stabilize before the first conversion. If the STOP mode is exited withno delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D circuitry to stabilizeto avoid invalid results.10.8 A/D Control/Status RegistersAll bits in this register can be read or written, except bit 7, which is a read-only statusindicator, and bit 6, which always reads as zero. Write to ADCTL to initiate a conversion. To quit a conversion in progress, write to this register and a new conversion sequence begins immediately.ADCTL — A/D Control/StatusRESET:Bit 7CCFI6—0$10305SCANI4MULTI3CDI2CCI1CBIBit 0CAICCF — Conversions Complete FlagA read-only status indicator, this bit is set when all four A/D result registers contain valid conversion results.
Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a conversion sequence is started. In the continuous mode,CCF is set at the end of the first conversion sequence.Bit 6 — Not implementedAlways reads zero.SCAN — Continuous Scan ControlWhen this control bit is clear, the four requested conversions are performed once tofill the four result registers.
When this control bit is set, conversions are performed continuously with the result registers updated as data becomes available.MULT — Multiple Channel/Single Channel ControlWhen this bit is clear, the A/D converter system is configured to perform four consecutive conversions on the single channel specified by the four channel select bitsCD:CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D system is configured to perform a conversion on each of four channels where each result registercorresponds to one channel.M68HC11 E SERIESTECHNICAL DATAANALOG-TO-DIGITAL CONVERTERMOTOROLA10-710NOTEWhen the multiple-channel continuous scan mode is used, extra careis needed in the design of circuitry driving the A/D inputs.
The chargeon the capacitive DAC array before the sample time is related to thevoltage on the previously converted channel. A charge share situation exists between the internal DAC capacitance and the externalcircuit capacitance. Although the amount of charge involved is small,the rate at which it is repeated is every 64 µs for an E clock of 2 MHz.The RC charging rate of the external circuit must be balanced againstthis charge sharing effect to avoid errors in accuracy. Refer toM68HC11 Reference Manual (M68HC11RM/AD) for further information.10CD:CA — Channel Selects D:ARefer to Table 10-2.
When a multiple channel mode is selected (MULT = 1), the twoleast significant channel select bits (CB and CA) have no meaning and the CD and CCbits specify which group of four channels is to be converted.Table 10-2 A/D Converter Channel SelectionChannel SelectControl BitsChannel SignalResult in ADRx ifMULT = 10000AN0ADR10001AN1ADR20010AN2ADR30011AN3ADR40100AN4ADR10101AN5ADR20110AN6ADR3CD:CC:CB:CA0111AN7ADR410XXReserved—1100VRH1ADR11101VRL1ADR21110(VRH)/21ADR31111Reserved1ADR4NOTES:1.
Used for factory testing10.9 A/D Converter Result RegistersThese read-only registers hold an 8-bit conversion result. Writes to these registershave no effect. Data in the A/D converter result registers is valid when the CCF flag inthe ADCTL register is set, indicating a conversion sequence is complete.
If conversionresults are needed sooner, refer to Figure 10-3, which shows the A/D conversion sequence diagram.MOTOROLA10-8ANALOG-TO-DIGITAL CONVERTERM68HC11 E SERIESTECHNICAL DATAADR[1:4] — A/D Results$1031 – $1034$1031Bit 7654321Bit 0ADR1$1032Bit 7654321Bit 0ADR2$1033Bit 7654321Bit 0ADR3$1034Bit 7654321Bit 0ADR410M68HC11 E SERIESTECHNICAL DATAANALOG-TO-DIGITAL CONVERTERMOTOROLA10-910MOTOROLA10-10ANALOG-TO-DIGITAL CONVERTERM68HC11 E SERIESTECHNICAL DATAAPPENDIX A ELECTRICAL CHARACTERISTICSTable A-1 Maximum RatingsRatingSupply VoltageInput VoltageOperating Temperature RangeMC68HC(7)11ExMC68HC(7)11ExCMC68HC(7)11ExVMC68HC(7)11ExMMC68HC811E2MC68HC811E2CMC68HC811E2VMC68HC811E2MMC68L11ExStorage Temperature RangeCurrent Drain per Pin1Excluding VDD, VSS, AVDD, VRH, and VRLSymbolVDDVinTAValue–0.3 to + 7.0–0.3 to + 7.0TL to TH0 to + 70–40 to + 85–40 to + 105–40 to + 1250 to + 70–40 to + 85–40 to + 105–40 to + 125–20 to + 70–55 to + 15025TstgIDUnitVV°CA°CmANOTES:1.
One pin at a time, observing maximum power dissipation limitsInternal circuitry protects the inputs against damage caused by high static voltages orelectric fields; however, normal precautions are necessary to avoid application of anyvoltage higher than maximum-rated voltages to this high-impedance circuit. Extendedoperation at the maximum ratings can adversely affect device reliability. Tying unusedinputs to an appropriate logic voltage level (either GND or VDD) enhances reliability ofoperation.Table A-2 Thermal CharacteristicsCharacteristicAverage Junction TemperatureAmbient TemperaturePackage Thermal Resistance (Junction-to-Ambient)48-Pin Plastic DIP (MC68HC811E2 only)56-Pin Plastic SDIP52-Pin Plastic Leaded Chip Carrier52-Pin Plastic Thin Quad Flat Pack (TQFP)64-Pin Quad Flat PackTotal Power Dissipation(Note 1)Device Internal Power DissipationI/O Pin Power DissipationA Constant(Note 2)(Note 3)SymbolTJTAΘJAPDPINTPI/OKValueTA + (PD × ΘJA)User-determinedUnit°C°C°C/W5050508585PINT + PI/OK / (TJ + 273°C) (Note 1)IDD × VDDUser-determinedPD × (TA + 273°C) +ΘJA × PD2WWWW⋅°CNOTES:1.
This is an approximate value, neglecting PI/O.2. For most applications neglected.3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium).Use this value of K to solve for PD and TJ iteratively for any value of TA.M68HC11 E SERIESTECHNICAL DATAELECTRICAL CHARACTERISTICSMOTOROLAA-1Table A-3 DC Electrical CharacteristicsVDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise notedCharacteristicsSymbolMinMaxUnitOutput Voltage (Note 1)All Outputs except XTALAll Outputs Except XTAL, RESET, and MODAILoad = ±10.0 µAV OLVOH—VDD –0.10.1—VOutput High Voltage (Note 1)All Outputs Except XTAL,RESET, and MODAVOHVDD –0.8—VOutput Low VoltageILoad = 1.6 mAAll Outputs Except XTALVOL—0.4VInput High VoltageAll Inputs Except RESETRESETVIH0.7 × VDD0.8 × VDDVDD + 0.3VDD + 0.3VInput Low VoltageAll InputsVILVSS –0.30.2 × VDDVPA7, PA3,PC[7:0], PD[5:0], AS/STRA,MODA/LIR, RESETIOZ—±10µAInput Leakage Current (Note 2)PA[2:0], IRQ, XIRQVin = VDD or VSSVin = VDD or VSSMODB/VSTBY(XIRQ on EPROM-based devices)Iin——±1±10µAµAVSB4.0VDDVILoad = –0.8 mA, VDD = 4.5 VI/O Ports, Three-State LeakageVin = VIH or VILARAM Standby VoltageePower downPower downISB—10µAPA[2:0], PE[7:0], IRQ, XIRQ, EXTALPA7, PA3, PC[7:0], PD[5:0],AS/STRA, MODA/LIR, RESETCin——812pFpFAll Outputs Except PD[4:1]PD[4:1]CL——90100pFpF————15272735mAmAmAmA————6151020mAmAmAmA———2550100µA————85150150195mWmWmWmWRAM Standby CurrentInput CapacitanceOutput Load CapacitanceMaximum Total Supply Current (Note 3)RUN:Single-Chip Mode2 MHz3 MHz2 MHz3 MHzExpanded Multiplexed ModeWAIT: (All Peripheral Functions Shut Down)Single-Chip ModeExpanded Multiplexed ModeSTOP:Single-Chip Mode, No ClocksMaximum Power DissipationSingle-Chip ModeExpanded Multiplexed Mode2 MHz3 MHz2 MHz3 MHz–40 to + 85> + 85 to + 105> +105 to + 1252 MHz3 MHz2 MHz3 MHzIDDWIDDSIDDPDNOTES:1.
VOH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specificationnot applicable to ports C and D in wired-OR mode.2. Refer to A/D specification for leakage current for port E.3. EXTAL is driven with a square wave, andtcyc = 500 ns for 2 MHz rating;tcyc = 333 ns for 3 MHz rating; VIL ≤0.2 V;VIH ≥VDD – 0.2 V; No dc loadsMOTOROLAA-2ELECTRICAL CHARACTERISTICSM68HC11 E SERIESTECHNICAL DATATable A-3a DC Electrical Characteristics (MC68L11E9)VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise notedCharacteristicOutput Voltage (Note 1)All Outputs except XTALAll Outputs Except XTAL, RESET, and MODAILoad = ±10.0 µAOutput High Voltage (Note 1)All Outputs Except XTAL,RESET, and MODAILoad = –0.5 mA, VDD = 3.0 VILoad = –0.8 mA, VDD = 4.5 VOutput Low VoltageAll Outputs Except XTALILoad = 1.6 mA, VDD = 5.0 VILoad = 1.0 mA, VDD = 3.0 VInput High VoltageAll Inputs Except RESETRESETInput Low Voltage All InputsI/O Ports, Three-State Leakage PA7, PA3,PC[7:0], PD[5:0], AS/STRA,Vin = VIH or VILMODA/LIR, RESETInput Leakage Current (Note 2)Vin = VDD or VSSPA[2:0], IRQ, XIRQVin = VDD or VSSMODB/VSTBY(XIRQ on EPROM-based devices)RAM Standby VoltagePower downRAM Standby CurrentPower downInput CapacitancePA[2:0], PE[7:0], IRQ, XIRQ, EXTALPA7, PA3, PC[7:0], PD[5:0],AS/STRA, MODA/LIR, RESETOutput Load CapacitanceAll Outputs Except PD[4:1]PD[4:1]SymbolVOLVOHMin—VDD –0.1Max0.1—UnitVVVOHVDD –0.8—VVOL—0.4VVIH0.7 × VDD0.8 × VDDVSS –0.3—VDD + 0.3VDD + 0.30.2 × VDD±10VVVµA——±1±10µAµAVSBISBCin2.0———VDD10812VµApFpFCL——90100pFpFCharacteristicMaximum Total Supply Current (Note 3)RUN:Single-Chip ModeSymbol1 MHz2 MHzUnit841471582714mAmAmAmA31.552.563105mAmAmAmA50255025µAµA44127721852415042mWmWmWmWExpanded Multiplexed ModeWAIT:(All Peripheral Functions Shut Down)Single-Chip ModeExpanded Multiplexed ModeSTOP:Single-Chip Mode, No ClocksMaximum Power DissipationSingle-Chip ModeExpanded Multiplexed ModeVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVDD = 5.5 VVDD = 3.0 VVILIOZIinIDDWIDDSIDDPDNOTES:1.
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