ATmega128 (Скамко)

Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture•••••••– 133 Powerful Instructions – Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers + Peripheral Control Registers– Fully Static Operation– Up to 16 MIPS Throughput at 16 MHz– On-chip 2-cycle MultiplierNonvolatile Program and Data Memories– 128K Bytes of In-System Reprogrammable FlashEndurance: 10,000 Write/Erase Cycles– Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation– 4K Bytes EEPROMEndurance: 100,000 Write/Erase Cycles– 4K Bytes Internal SRAM– Up to 64K Bytes Optional External Memory Space– Programming Lock for Software Security– SPI Interface for In-System ProgrammingJTAG (IEEE std.

1149.1 Compliant) Interface– Boundary-scan Capabilities According to the JTAG Standard– Extensive On-chip Debug Support– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG InterfacePeripheral Features– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode andCapture Mode– Real Time Counter with Separate Oscillator– Two 8-bit PWM Channels– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits– Output Compare Modulator– 8-channel, 10-bit ADC8 Single-ended Channels7 Differential Channels2 Differential Channels with Programmable Gain at 1x, 10x, or 200x– Byte-oriented Two-wire Serial Interface– Dual Programmable Serial USARTs– Master/Slave SPI Serial Interface– Programmable Watchdog Timer with On-chip Oscillator– On-chip Analog ComparatorSpecial Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,and Extended Standby– Software Selectable Clock Frequency– ATmega103 Compatibility Mode Selected by a Fuse– Global Pull-up DisableI/O and Packages– 53 Programmable I/O Lines– 64-lead TQFP and 64-pad MLFOperating Voltages– 2.7 - 5.5V for ATmega128L– 4.5 - 5.5V for ATmega128Speed Grades– 0 - 8 MHz for ATmega128L– 0 - 16 MHz for ATmega1288-bitMicrocontrollerwith 128K BytesIn-SystemProgrammableFlashATmega128ATmega128LRev.

2467M–AVR–11/04Figure 1. Pinout ATmega128484746454443424140393837363534331718192021222324252627282930313212345678910111213141516PA3 (AD3)PA4 (AD4)PA5 (AD5)PA6 (AD6)PA7 (AD7)PG2(ALE)PC7 (A15)PC6 (A14)PC5 (A13)PC4 (A12)PC3 (A11)PC2 (A10)PC1 (A9)PC0 (A8)PG1(RD)PG0(WR)(OC2/OC1C) PB7TOSC2/PG3TOSC1/PG4RESETVCCGNDXTAL2XTAL1(SCL/INT0) PD0(SDA/INT1) PD1(RXD1/INT2) PD2(TXD1/INT3) PD3(ICP1) PD4(XCK1) PD5(T1) PD6(T2) PD7PENRXD0/(PDI) PE0(TXD0/PDO) PE1(XCK0/AIN0) PE2(OC3A/AIN1) PE3(OC3B/INT4) PE4(OC3C/INT5) PE5(T3/INT6) PE6(ICP3/INT7) PE7(SS) PB0(SCK) PB1(MOSI) PB2(MISO) PB3(OC0) PB4(OC1A) PB5(OC1B) PB664636261605958575655545352515049AVCCGNDAREFPF0 (ADC0)PF1 (ADC1)PF2 (ADC2)PF3 (ADC3)PF4 (ADC4/TCK)PF5 (ADC5/TMS)PF6 (ADC6/TDO)PF7 (ADC7/TDI)GNDVCCPA0 (AD0)PA1 (AD1)PA2 (AD2)Pin ConfigurationsNote:Overview2The bottom pad under the MLF package should be soldered to ground.The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture.

By executing powerful instructions in a single clock cycle,the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.ATmega1282467M–AVR–11/04ATmega128Block DiagramPC0 - PC7PA0 - PA7RESETXTAL1PF0 - PF7XTAL2Figure 2. Block DiagramVCCGNDPORTA DRIVERSPORTF DRIVERSDATA DIR.REG. PORTFDATA REGISTERPORTFPORTC DRIVERSDATA DIR.REG.

PORTADATA REGISTERPORTADATA REGISTERPORTCDATA DIR.REG. PORTC8-BIT DATA BUSAVCCCALIB. OSCINTERNALOSCILLATORADCAGNDAREFOSCILLATORPROGRAMCOUNTERSTACKPOINTERWATCHDOGTIMERON-CHIP DEBUGPROGRAMFLASHSRAMMCU CONTROLREGISTERBOUNDARYSCANINSTRUCTIONREGISTERJTAG TAPOSCILLATORTIMING ANDCONTROLTIMER/COUNTERSGENERALPURPOSEREGISTERSXPENPROGRAMMINGLOGICINSTRUCTIONDECODERCONTROLLINESZINTERRUPTUNITALUEEPROMYSTATUSREGISTERSPI+-ANALOGCOMPARATORUSART0DATA REGISTERPORTEDATA DIR.REG. PORTEPORTE DRIVERSPE0 - PE7DATA REGISTERPORTBDATA DIR.REG.

PORTBPORTB DRIVERSPB0 - PB7USART1DATA REGISTERPORTDTWO-WIRE SERIALINTERFACEDATA DIR.REG. PORTDDATA REG.PORTGDATA DIR.REG. PORTGPORTD DRIVERSPORTG DRIVERSPD0 - PD7PG0 - PG432467M–AVR–11/04The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle. The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53general purpose I/O lines, 32 general purpose working registers, Real Time Counter(RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byteoriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differentialinput stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.

1149.1 compliant JTAG test interface, also used foraccessing the On-chip Debug system and programming and six software selectablepower saving modes. The Idle mode stops the CPU while allowing the SRAM,Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all otherchip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while therest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and allI/O modules except Asynchronous Timer and ADC, to minimize switching noise duringADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running whilethe rest of the device is sleeping.

This allows very fast start-up combined with low powerconsumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.The device is manufactured using Atmel’s high-density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-systemthrough an SPI serial interface, by a conventional nonvolatile memory programmer, orby an On-chip Boot program running on the AVR core.

The boot program can use anyinterface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPUwith In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 isa powerful microcontroller that provides a highly flexible and cost effective solution tomany embedded control applications.The ATmega128 AVR is supported with a full suite of program and system developmenttools including: C compilers, macro assemblers, program debugger/simulators, in-circuitemulators, and evaluation kits.ATmega103 andATmega128Compatibility4The ATmega128 is a highly complex microcontroller where the number of I/O locationssupersedes the 64 I/O locations reserved in the AVR instruction set.

To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 havethe same location in ATmega128. Most additional I/O locations are added in anExtended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAMspace). These locations can be reached by using LD/LDS/LDD and ST/STS/STDinstructions only, not by using IN and OUT instructions.

The relocation of the internalRAM space may still be a problem for ATmega103 users. Also, the increased number ofinterrupt vectors might be a problem if the code uses absolute addresses. To solvethese problems, an ATmega103 compatibility mode can be selected by programmingthe fuse M103C.

In this mode, none of the functions in the Extended I/O space are inuse, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.ATmega1282467M–AVR–11/04ATmega128The ATmega128 is 100% pin compatible with ATmega103, and can replace theATmega103 on current Printed Circuit Boards. The application note “ReplacingATmega103 by ATmega128” describes what the user should be aware of replacing theATmega103 by an ATmega128.ATmega103 CompatibilityModeBy programming the M103C fuse, the ATmega128 will be compatible with theATmega103 regards to RAM, I/O pins and interrupt vectors as described above.

However, some new features in ATmega128 are not available in this compatibility mode,these features are listed below:•One USART instead of two, Asynchronous mode only. Only the eight leastsignificant bits of the Baud Rate Register is available.•One 16 bits Timer/Counter with two compare registers instead of two 16-bitTimer/Counters with three compare registers.•Two-wire serial interface is not supported.•Port C is output only.•Port G serves alternate functions only (not a general I/O port).•Port F serves as digital input only in addition to analog input to the ADC.•Boot Loader capabilities is not supported.•It is not possible to adjust the frequency of the internal calibrated RC Oscillator.•The External Memory Interface can not release any Address pins for general I/O,neither configure different wait-states to different External Memory Addresssections.In addition, there are some other minor differences to make it more compatible toATmega103:•Only EXTRF and PORF exists in MCUCSR.•Timed sequence not required for Watchdog Time-out change.•External Interrupt pins 3 - 0 serve as level interrupt only.•USART has no FIFO buffer, so data overrun comes earlier.Unused I/O bits in ATmega103 should be written to 0 to ensure same operation inATmega128.Pin DescriptionsVCCDigital supply voltage.GNDGround.Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit).