ATmega8 (961722), страница 47
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Set BS1 and BS2 to “0”.4. Give WR a negative pulse and wait for RDY/BSY to go high.2292486O–AVR–10/04Programming the Fuse HighBitsThe algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe Flash” on page 226 for details on Command and Data loading):1. A: Load Command “0100 0000”.2. C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.3.
Set BS1 to “1” and BS2 to “0”. This selects high data byte.4. Give WR a negative pulse and wait for RDY/BSY to go high.5. Set BS1 to “0”. This selects low data byte.Programming the Lock BitsThe algorithm for programming the Lock Bits is as follows (refer to “Programming theFlash” on page 226 for details on Command and Data loading):1.
A: Load Command “0010 0000”.2. C: Load Data Low byte. Bit n = “0” programs the Lock bit.3. Give WR a negative pulse and wait for RDY/BSY to go high.The Lock Bits can only be cleared by executing Chip Erase.Reading the Fuse and LockBitsThe algorithm for reading the Fuse and Lock Bits is as follows (refer to “Programmingthe Flash” on page 226 for details on Command loading):1. A: Load Command “0000 0100”.2. Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits cannow be read at DATA (“0” means programmed).3.
Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits cannow be read at DATA (“0” means programmed).4. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now beread at DATA (“0” means programmed).5. Set OE to “1”.Figure 108. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During Read0Fuse low byteDATALock bits01Fuse high byte1BS1BS2230ATmega8(L)2486O–AVR–10/04ATmega8(L)Reading the Signature BytesThe algorithm for reading the Signature bytes is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 1000”.2. B: Load Address Low byte (0x00 - 0x02).3. Set OE to “0”, and BS1 to “0”.
The selected Signature byte can now be read atDATA.4. Set OE to “1”.Reading the Calibration ByteThe algorithm for reading the Calibration bytes is as follows (refer to “Programming theFlash” on page 226 for details on Command and Address loading):1. A: Load Command “0000 1000”.2. B: Load Address Low byte, (0x00 - 0x03).3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.4. Set OE to “1”.Parallel ProgrammingCharacteristicsFigure 109.
Parallel Programming Timing, Including some General TimingRequirementst XLWLt XHXLXTAL1t DVXHt XLDXData & Contol(DATA, XA0/1, BS1, BS2)t PLBXt BVPHPAGELt BVWLt WLBXt PHPLt WLWRWHt PLWLWLRLRDY/BSYt WLRHFigure 110. Parallel Programming Timing, Loading Sequence with TimingRequirements(1)LOAD ADDRESS(LOW BYTE)LOAD DATA LOAD DATA(HIGH BYTE)LOAD DATA(LOW BYTE)t XLXHtXLPHLOAD ADDRESS(LOW BYTE)tPLXHXTAL1BS1PAGELDATAADDR0 (Low Byte)DATA (Low Byte)DATA (High Byte)ADDR1 (Low Byte)XA0XA1Note:1. The timing requirements shown in Figure 109 (i.e., tDVXH, tXHXL, and tXLDX) also applyto loading operation.2312486O–AVR–10/04Figure 111.
Parallel Programming Timing, Reading Sequence (within the same Page)with Timing Requirements(1)LOAD ADDRESS(LOW BYTE)READ DATA(LOW BYTE)READ DATA(HIGH BYTE)LOAD ADDRESS(LOW BYTE)tXLOLXTAL1tBVDVBS1tOLDVOEtOHDZDATAADDR0 (Low Byte)ADDR1 (Low Byte)DATA (High Byte)DATA (Low Byte)XA0XA1Note:1. The timing requirements shown in Figure 109 (i.e., tDVXH, tXHXL, and tXLDX) also applyto reading operation.Table 95.
Parallel Programming Characteristics, VCC = 5V ± 10%232SymbolParameterMinVPPProgramming Enable Voltage11.5IPPProgramming Enable CurrenttDVXHData and Control Valid before XTAL1 High67nstXLXHXTAL1 Low to XTAL1 High200nstXHXLXTAL1 Pulse Width High150nstXLDXData and Control Hold after XTAL1 Low67nstXLWLXTAL1 Low to WR Low0nstXLPHXTAL1 Low to PAGEL high0nstPLXHPAGEL low to XTAL1 high150nstBVPHBS1 Valid before PAGEL High67nstPHPLPAGEL Pulse Width High150nstPLBXBS1 Hold after PAGEL Low67nstWLBXBS2/1 Hold after WR Low67nstPLWLPAGEL Low to WR Low67nstBVWLBS1 Valid to WR Low67nstWLWHWR Pulse Width Low150nstWLRLWR Low to RDY/BSY LowtWLRHWR Low to RDY/BSY High(1)(2)tWLRH_CEWR Low to RDY/BSY High for Chip ErasetXLOLXTAL1 Low to OE LowTypMaxUnits12.5V250µA01µs3.74.5ms7.59ms0nsATmega8(L)2486O–AVR–10/04ATmega8(L)Table 95.
Parallel Programming Characteristics, VCC = 5V ± 10% (Continued)SymbolParametertBVDVBS1 Valid to DATA validtOLDVtOHDZNotes:MinMaxUnits250nsOE Low to DATA Valid250nsOE High to DATA Tri-stated250ns0Typ1.tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write LockBits commands.2.
tWLRH_CE is valid for the Chip Erase command.2332486O–AVR–10/04Serial DownloadingSerial Programming PinMappingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI(input) and MISO (output). After RESET is set low, the Programming Enable instructionneeds to be executed first before program/erase operations can be executed.
NOTE, inTable 96 on page 234, the pin mapping for SPI programming is listed. Not all parts usethe SPI pins dedicated for the internal SPI interface.Table 96. Pin Mapping Serial ProgrammingSymbolPinsI/ODescriptionMOSIPB3ISerial data inMISOPB4OSerial data outSCKPB5ISerial clockFigure 112. Serial Programming and Verify(1)+2.7 - 5.5VVCCMOSIPB3MISOPB4SCKPB5+2.7 - 5.5V (2)AVCCXTAL1RESETGNDNotes:1. If the device is clocked by the Internal Oscillator, it is no need to connect a clocksource to the XTAL1 pin.2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute theChip Erase instruction.
The Chip Erase operation turns the content of every memorylocation in both the Program and EEPROM arrays into 0xFF.Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the Serial Clock (SCK) input are defined as follows:Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHzHigh:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz234ATmega8(L)2486O–AVR–10/04ATmega8(L)Serial ProgrammingAlgorithmWhen writing serial data to the ATmega8, data is clocked on the rising edge of SCK.When reading data from the ATmega8, data is clocked on the falling edge of SCK.
SeeFigure 113 for timing details.To program and verify the ATmega8 in the Serial Programming mode, the followingsequence is recommended (See four byte instruction formats in Table 98):1. Power-up sequence:Apply power between VCC and GND while RESET and SCK are set to “0”. Insome systems, the programmer can not guarantee that SCK is held low duringPower-up. In this case, RESET must be given a positive pulse of at least twoCPU clock cycles duration after SCK has been set to “0”.2. Wait for at least 20 ms and enable Serial Programming by sending the Programming Enable serial instruction to pin MOSI.3.
The Serial Programming instructions will not work if the communication is out ofsynchronization. When in sync. the second byte (0x53), will echo back whenissuing the third byte of the Programming Enable instruction. Whether the echois correct or not, all four bytes of the instruction must be transmitted. If the 0x53did not echo back, give RESET a positive pulse and issue a new ProgrammingEnable command.4. The Flash is programmed one page at a time. The page size is found in Table 89on page 222.
The memory page is loaded one byte at a time by supplying the 5LSB of the address and data together with the Load Program memory Pageinstruction. To ensure correct loading of the page, the data Low byte must beloaded before data High byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction withthe 7 MSB of the address.
If polling is not used, the user must wait at leasttWD_FLASH before issuing the next page. (See Table 97).Note: If other commands than polling (read) are applied before any write operation(FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrectprogramming.5. The EEPROM array is programmed one byte at a time by supplying the addressand data together with the appropriate Write instruction. An EEPROM memorylocation is first automatically erased before new data is written. If polling is notused, the user must wait at least tWD_EEPROM before issuing the next byte.
(SeeTable 97 on page 236). In a chip erased device, no 0xFFs in the data file(s) needto be programmed.6. Any memory location can be verified by using the Read instruction which returnsthe content at the selected address at serial output MISO.7. At the end of the programming session, RESET can be set high to commencenormal operation.8. Power-off sequence (if needed):Set RESET to “1”.Turn VCC power offData Polling FlashWhen a page is being programmed into the Flash, reading an address location withinthe page being programmed will give the value 0xFF.
At the time the device is ready fora new page, the programmed value will read correctly. This is used to determine whenthe next page can be written. Note that the entire page is written simultaneously and anyaddress within the page can be used for polling. Data polling of the Flash will not workfor the value 0xFF, so when programming this value, the user will have to wait for atleast tWD_FLASH before programming the next page. As a chip-erased device contains2352486O–AVR–10/040xFF in all locations, programming of addresses that are meant to contain 0xFF, can beskipped.
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