ATmega8 (961722), страница 51
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Calibrated 8 MHz RC Oscillator Frequency vs. Osccal ValueCALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE1614FRC (MHz)12108640163248648096112128144160176192208224240OSCCAL VALUE2732486O–AVR–10/04Figure 173. Calibrated 4 MHz RC Oscillator Frequency vs. TemperatureCALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE4.25.5V4.14.0VFRC (MHz)43.92.7V3.83.73.63.5-60-40-20020406080100Temperature (˚C)Figure 174. Calibrated 4 MHz RC Oscillator Frequency vs.
VCCCALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC4.2-40°C4.125°C4FRC (MHz)85°C3.93.83.73.63.52.533.544.555.5VCC (V)274ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 175. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal ValueCALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE87FRC (MHz)654320163248648096112128144160176192208224240OSCCAL VALUEFigure 176. Calibrated 2 MHz RC Oscillator Frequency vs.
TemperatureCALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE2.15.5V2.054.0VFRC (MHz)21.952.7V1.91.851.8-60-40-20020406080100Temperature (˚C)2752486O–AVR–10/04Figure 177. Calibrated 2 MHz RC Oscillator Frequency vs. VCCCALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC2.22.1-40°CFRC (MHz)25°C285°C1.91.81.72.533.544.555.5VCC (V)Figure 178. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal ValueCALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE3.83.3FRC (MHz)2.82.31.81.30.80163248648096112128144160176192208224240OSCCAL VALUE276ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 179.
Calibrated 1 MHz RC Oscillator Frequency vs. TemperatureCALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE1.045.5V1.024.0VFRC (MHz)10.982.7V0.960.940.920.9-60-40-20020406080100Temperature (˚C)Figure 180. Calibrated 1 MHz RC Oscillator Frequency vs. VCCCALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC1.11.05FRC (MHz)-40°C25°C185°C0.950.92.533.544.555.5VCC (V)2772486O–AVR–10/04Figure 181. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal ValueCALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE1.91.7FRC (MHz)1.51.31.10.90.70.50163248648096112128144160176192208224240OSCCAL VALUECurrent Consumption ofPeripheral UnitsFigure 182.
Brown-out Detector Current vs. VCCBROWN-OUT DETECTOR CURRENT vs. VCC3025-40°C25°C85°CICC (uA)201510502.533.544.555.5VCC (V)278ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 183. ADC Current vs. VCC (AREF = AVCC)ADC CURRENT vs. VCCAREF = AVCC45040025°C-40°C35085°CICC (uA)3002502001501005002.533.544.555.5VCC (V)Figure 184. AREF External Reference Current vs. VCCAREF EXTERNAL REFERENCE CURRENT vs.
V CC25085°C20025°C-40°CICC (uA)1501005002.533.544.555.5VCC (V)2792486O–AVR–10/04Figure 185. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled)32 kHz TOSC CURRENT vs. V CCWATCHDOG TIMER DISABLED252025°CICC (uA)1510502.533.544.555.5VCC (V)Figure 186. Watchdog Timer Current vs. VCCWATCHDOG TIMER CURRENT vs. V CC807085°C60-40°C25°CICC (uA)5040302010022.533.544.555.5VCC (V)280ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 187. Analog Comparator Current vs.
VCCANALOG COMPARATOR CURRENT vs. VCC10085°C9025°C80-40°C70ICC (uA)60504030201002.533.544.555.5VCC (V)Figure 188. Programming Current vs. VCCPROGRAMMING CURRENT vs. VCC7-40°C625°CICC (mA)585°C432102.533.544.555.5VCC (V)2812486O–AVR–10/04Current Consumption inReset and Reset PulsewidthFigure 189. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current ThroughThe Reset Pull-up)RESET SUPPLY CURRENT vs. VCC0.1 - 1 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP45.5V3.55.0V34.5VICC (mA)2.54.0V23.3V3.0V2.7V1.510.5000.10.20.30.40.50.60.70.80.91Frequency (MHz)Figure 190. Reset Supply Current vs.
VCC (1 - 20 MHz, Excluding Current Through TheReset Pull-up)RESET SUPPLY CURRENT vs. VCC1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP255.5V205.0VICC (mA)4.5V15103.3V53.0V2.7V002468101214161820Frequency (MHz)282ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 191.
Reset Pulse Width vs. VCCRESET PULSE WIDTH vs. VCC14001200Pulsewidth (ns)100080060085°C25°C400-40°C20002.533.544.555.5VCC (V)2832486O–AVR–10/04Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 00x3F (0x5F)SREGITHSVNZCPage90x3E (0x5E)SPH–––––SP10SP9SP8110x3D (0x5D)SPLSP7SP6SP5SP4SP3SP2SP1SP0110x3C (0x5C)Reserved0x3B (0x5B)GICRINT1INT0––––IVSELIVCE47, 650x3A (0x5A)GIFRINTF1INTF0––––––660x39 (0x59)TIMSKOCIE2TOIE2TICIE1OCIE1AOCIE1BTOIE1–TOIE070, 100, 12071, 101, 1200x38 (0x58)TIFROCF2TOV2ICF1OCF1AOCF1BTOV1–TOV00x37 (0x57)SPMCRSPMIERWWSB–RWWSREBLBSETPGWRTPGERSSPMEN2100x36 (0x56)TWCRTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1680x35 (0x55)MCUCRSESM2SM1SM0ISC11ISC10ISC01ISC0031, 640x34 (0x54)MCUCSR––––WDRFBORFEXTRFPORF390x33 (0x53)TCCR0–––––CS02CS01CS00700x32 (0x52)TCNT0Timer/Counter0 (8 Bits)0x31 (0x51)OSCCALOscillator Calibration Register0x30 (0x50)SFIOR––––7029ACMEPUDPSR2PSR1056, 73, 121, 1900x2F (0x4F)TCCR1ACOM1A1COM1A0COM1B1COM1B0FOC1AFOC1BWGM11WGM10950x2E (0x4E)TCCR1BICNC1ICES1–WGM13WGM12CS12CS11CS10980x2D (0x4D)TCNT1HTimer/Counter1 – Counter Register High byte990x2C (0x4C)TCNT1L990x2B (0x4B)OCR1AHTimer/Counter1 – Counter Register Low byteTimer/Counter1 – Output Compare Register A High byte990x2A (0x4A)OCR1ALTimer/Counter1 – Output Compare Register A Low byte990x29 (0x49)OCR1BHTimer/Counter1 – Output Compare Register B High byte990x28 (0x48)OCR1BLTimer/Counter1 – Output Compare Register B Low byte990x27 (0x47)ICR1HTimer/Counter1 – Input Capture Register High byte1000x26 (0x46)ICR1L0x25 (0x45)TCCR20x24 (0x44)TCNT20x23 (0x43)OCR2Timer/Counter1 – Input Capture Register Low byteFOC2WGM20COM21COM20WGM21100CS22CS21CS20Timer/Counter2 (8 Bits)Timer/Counter2 Output Compare Register1171170x22 (0x42)ASSR––––AS2TCN2UBOCR2UBTCR2UB0x21 (0x41)WDTCR–––WDCEWDEWDP2WDP1WDP0UBRRHURSEL–––0x20(1) (0x40)(1)115UBRR[11:8]11741155UCSRCURSELUMSELUPM1UPM0USBSUCSZ1UCSZ0UCPOL0x1F (0x3F)EEARH–––––––EEAR8180x1E (0x3E)EEARLEEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0180x1D (0x3D)EEDR0x1C (0x3C)EECR––––EERIEEEMWEEEWEEERE0x1B (0x3B)Reserved0x1A (0x3A)Reserved0x19 (0x39)Reserved0x18 (0x38)PORTBPORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0630x17 (0x37)DDRBDDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0630x16 (0x36)PINBPINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0630x15 (0x35)PORTC–PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0630x14 (0x34)DDRC–DDC6DDC5DDC4DDC3DDC2DDC1DDC0630x13 (0x33)PINC–PINC6PINC5PINC4PINC3PINC2PINC1PINC0630x12 (0x32)PORTDPORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0630x11 (0x31)DDRDDDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0630x10 (0x30)PINDPIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND00x0F (0x2F)SPDREEPROM Data Register15318SPI Data Register18631280x0E (0x2E)SPSRSPIFWCOL–––––SPI2X1280x0D (0x2D)SPCRSPIESPEDORDMSTRCPOLCPHASPR1SPR01260x0C (0x2C)UDR0x0B (0x2B)UCSRARXCTXCUDRE0x0A (0x2A)UCSRBRXCIETXCIEUDRIE0x09 (0x29)UBRRL0x08 (0x28)ACSRACDACBGACOUSART I/O Data Register150FEDORPEU2XMPCM151RXENTXENUCSZ2RXB8TXB8152ACICACIS1ACIS0191USART Baud Rate Register Low byteACIACIE1550x07 (0x27)ADMUXREFS1REFS0ADLAR–MUX3MUX2MUX1MUX02020x06 (0x26)ADCSRAADENADSCADFRADIFADIEADPS2ADPS1ADPS02040x05 (0x25)ADCHADC Data Register High byte2050x04 (0x24)ADCLADC Data Register Low byte2050x03 (0x23)TWDR0x02 (0x22)TWAR284Two-wire Serial Interface Data RegisterTWA6TWA5TWA4TWA3TWA2170TWA1TWA0TWGCE170ATmega8(L)2486O–AVR–10/04ATmega8(L)Register Summary (Continued)AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x01 (0x21)TWSRTWS7TWS6TWS5TWS4TWS3–TWPS1TWPS01700x00 (0x20)TWBRNotes:Two-wire Serial Interface Bit Rate Register1681.
Refer to the USART description for details on how to access UBRRH and UCSRC.2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate onall bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag.
The CBI and SBI instructionswork with registers 0x00 to 0x1F only.2852486O–AVR–10/04Instruction Set SummaryMnemonicsOperandsDescriptionOperationFlags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,HADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1SUBIRd, KSubtract Constant from RegisterRd ← Rd - KZ,C,N,V,H1SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H11SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S21ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,VANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1INCRdIncrementRd ← Rd + 1Z,N,V1DECRdDecrementRd ← Rd − 1Z,N,V1TSTRdTest for Zero or MinusRd ← Rd • RdZ,N,V1CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1SERRdSet RegisterRd ← 0xFFNone1MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) <<Z,C2FMULSRd, RrFractional Multiply SignedZ,C2FMULSURd, RrFractional Multiply Signed with Unsigned1R1:R0 ← (Rd x Rr) << 1R1:R0 ← (Rd x Rr) << 1Z,C2Relative JumpPC ← PC + k + 1None2Indirect Jump to (Z)PC ← ZNone2BRANCH INSTRUCTIONSRJMPkIJMPRelative Subroutine CallPC ← PC + k + 1None3ICALLIndirect Call to (Z)PC ← ZNone3RETSubroutine ReturnPC ← STACKNone4RETIInterrupt ReturnPC ← STACKIif (Rd = Rr) PC ← PC + 2 or 3NoneRCALLk4CPSERd,RrCompare, Skip if Equal1/2/3CPRd,RrCompareRd − RrZ, N,V,C,H1CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,HSBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3None11/2/3SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3None1/2/3SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2BREQkBranch if Equalif (Z = 1) then PC ← PC + k + 1None1/2BRNEkBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2BRCSkBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2BRCCkBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2BRSHkBranch if Same or Higherif (C = 0) then PC ← PC + k + 1None1/2BRLOkBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2BRMIkBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2BRPLkBranch if Plusif (N = 0) then PC ← PC + k + 1None1/2BRGEkBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2BRLTkBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2BRHSkBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2BRHCkBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2BRTSkBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2BRTCkBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2BRVSkBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2BRVCkBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1NoneMnemonics286OperandsDescriptionOperationFlags1/2#ClocksATmega8(L)2486O–AVR–10/04ATmega8(L)Instruction Set Summary (Continued)BRIEkBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2BRIDkBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2None1None1DATA TRANSFER INSTRUCTIONSMOVRd, RrMove Between RegistersMOVWRd, RrCopy Register WordRd ← RrRd+1:Rd ← Rr+1:RrLDIRd, KLoad ImmediateRd ← KNone1LDRd, XLoad IndirectRd ← (X)None2LDRd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2LDRd, - XLoad Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None22LDRd, YLoad IndirectRd ← (Y)NoneLDRd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2LDRd, - YLoad Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None2LDDRd,Y+qLoad Indirect with DisplacementRd ← (Y + q)None2LDRd, ZLoad IndirectRd ← (Z)None2LDRd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2LDRd, -ZLoad Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None22LDSRd, kLoad Direct from SRAMRd ← (k)NoneSTX, RrStore Indirect(X) ← RrNone2STX+, RrStore Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2ST- X, RrStore Indirect and Pre-Dec.X ← X - 1, (X) ← RrNone2STY, RrStore Indirect(Y) ← RrNone2STY+, RrStore Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2ST- Y, RrStore Indirect and Pre-Dec.Y ← Y - 1, (Y) ← RrNone2STDY+q,RrStore Indirect with Displacement(Y + q) ← RrNone2STZ, RrStore Indirect(Z) ← RrNone2STZ+, RrStore Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None2ST-Z, RrStore Indirect and Pre-Dec.Z ← Z - 1, (Z) ← RrNone2STDZ+q,RrStore Indirect with Displacement(Z + q) ← RrNone2STSk, RrStore Direct to SRAM(k) ← RrNone2Load Program MemoryR0 ← (Z)None3LPMLPMRd, ZLoad Program MemoryRd ← (Z)None3LPMRd, Z+Load Program Memory and Post-IncRd ← (Z), Z ← Z+1None3Store Program Memory(Z) ← R1:R0None-In PortRd ← PNone1SPMINRd, POUTP, RrOut PortP ← RrNone1PUSHRrPush Register on StackSTACK ← RrNone2POPRdPop Register from StackRd ← STACKNone2BIT AND BIT-TEST INSTRUCTIONSSBIP,bSet Bit in I/O RegisterI/O(P,b) ← 1None2CBIP,bClear Bit in I/O RegisterI/O(P,b) ← 0None2LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1ROLRdRotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Z,C,N,V1RORRdRotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n=0..6Z,C,N,V1SWAPRdSwap NibblesRd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None1BSETsFlag SetSREG(s) ← 1SREG(s)1BCLRsFlag ClearSREG(s) ← 0SREG(s)1BSTRr, bBit Store from Register to TT ← Rr(b)T1BLDRd, bBit load from T to RegisterRd(b) ← TNone11SECSet CarryC←1CCLCClear CarryC←0C1SENSet Negative FlagN←1N1CLNClear Negative FlagN←0N1SEZSet Zero FlagZ←1Z1CLZClear Zero FlagZ←0Z1SEIGlobal Interrupt EnableI←1I1CLIGlobal Interrupt DisableI←0I11SESSet Signed Test FlagS←1SCLSClear Signed Test FlagS←0S1SEVSet Twos Complement Overflow.V←1V1CLVClear Twos Complement OverflowV←0V1SETSet T in SREGT←1TMnemonicsOperandsDescriptionOperation1Flags#Clocks2872486O–AVR–10/04Instruction Set Summary (Continued)CLTClear T in SREGT←0T1SEHCLHSet Half Carry Flag in SREGClear Half Carry Flag in SREGH←1H←0HH11MCU CONTROL INSTRUCTIONSNOPSLEEPWDRNo OperationSleepWatchdog Reset(see specific descr.
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