lab5 (774798), страница 6
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(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
Y 1 0 0 4 FB1_16 STD 22 I/O O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: C 3: Q.PIN 5: Q.PIN
2: PRE 4: Q.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Q XX...................................... 2 2
Y ..XXX................................... 3 3
Y ..XXX................................... 3 3
Y ..XXX................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 7/29
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
Q 4 0 0 1 FB2_1 STD 1 I/O I/O
(unused) 0 0 0 5 FB2_2 44 I/O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O I
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O GSR
(unused) 0 0 0 5 FB2_7 38 I/O
(unused) 0 0 0 5 FB2_8 37 I/O
(unused) 0 0 0 5 FB2_9 36 I/O I
(unused) 0 0 0 5 FB2_10 35 I/O I
Q 4 0 0 1 FB2_11 STD 34 I/O I/O
(unused) 0 0 0 5 FB2_12 33 I/O
(unused) 0 0 0 5 FB2_13 29 I/O
(unused) 0 0 0 5 FB2_14 28 I/O
(unused) 0 0 0 5 FB2_15 27 I/O
(unused) 0 0 0 5 FB2_16 26 I/O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: CLR 4: PRE 6: Q.PIN
2: CLR 5: PRE 7: Q.PIN
3: C
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Q X.XX.X.................................. 4 4
Q .XX.XXX................................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FTCPE FTCPE_Q1 (Q[1],1'b1,C,CLR,PRE[1]);
FTCPE FTCPE_Q2 (Q[2],Q[1].PIN,C,CLR[2],PRE[2]);
FTCPE FTCPE_Q3 (Q[3],Q_T[3],C,CLR[3],PRE[3]);
assign Q_T[3] = (Q[1].PIN && Q[2].PIN);
assign Y[1] = ((Q[1].PIN && Q[2].PIN)
|| (Q[2].PIN && !Q[3].PIN));
assign Y[2] = ((!Q[1].PIN && Q[3].PIN)
|| (!Q[2].PIN && !Q[3].PIN));
assign Y[3] = (Q[1].PIN && !Q[2].PIN && Q[3].PIN);
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9536-5-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9536-5-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 Q 23 GND
2 TIE 24 TIE
3 Q 25 TIE
4 TIE 26 TIE
5 TIE 27 TIE
6 TIE 28 TIE
7 TIE 29 TIE
8 CLR 30 TDO
9 Y 31 GND
10 GND 32 VCC
11 PRE 33 TIE
12 PRE 34 Q
13 TIE 35 PRE
14 Y 36 CLR
15 TDI 37 TIE
16 TMS 38 TIE
17 TCK 39 CLR
18 TIE 40 TIE
19 TIE 41 VCC
20 TIE 42 TIE
21 VCC 43 C
22 Y 44 TIE
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9536-5-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
После проведения трассировки и размещения результаты моделирования можно просмотреть с помощью View Fitter Design (ChipViewer):
Содержание отчета о временных характеристиках:
Timing Report
Need help reading this report?
| Design Name | var13 |
| Device, Speed (SpeedFile Version) | XC9536, -5 (3.0) |
| Date Created | Mon Jan 30 04:58:51 2006 |
| Created By | Timing Report Generator: version G.35 |
| Copyright | Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. |
Summary
| Performance Summary | |
| Min. Clock Period | 8.000 ns. |
| Max. Clock Frequency (fSYSTEM) | 125.000 MHz. |
| Limited by Clock Pulse Width for C | |
| Clock to Setup (tCYC) | 7.500 ns. |
| Clock Pad to Output Pad Delay (tCO) | 12.000 ns. |
Timing Constraints
| Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
| TS1000 | 30.0 | 0.0 | 0 | 0 |
Constraint: TS1000
| Description: PERIOD:PERIOD_C:30.000nS:HIGH:50.000000:% | |||
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
Number of constraints not met: 0
Data Sheet Report
Maximum External Clock Speeds
| Clock | fEXT (MHz) | Reason |
| C | 125.000 | Limited by Clock Pulse Width for C |
Setup/Hold Times for Clocks
Clock to Pad Timing
| Clock C to Pad | |
| Destination Pad | Clock (edge) to Pad |
| Y | 12.000 |
| Y | 12.000 |
| Y | 12.000 |
| Q | 7.000 |
| Q | 7.000 |
| Q | 7.000 |
Clock to Setup Times for Clocks
| Clock to Setup for clock C | ||
| Source | Destination | Delay |
| Q.Q | Q.D | 7.500 |
| Q.Q | Q.D | 7.500 |
| Q.Q | Q.D | 7.500 |
Pad to Pad List
| Source Pad | Destination Pad | Delay |
Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Mon Jan 30 04:58:51 2006
Функциональная модель, описанная с помощью языка Verilog:
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