DE0_Nano_User_Manual_v1.9 (1162595), страница 5

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Using adevelopment board helps you to verify whether your design is really working.■ You have gone through the quick start guide and/or the getting started user guide for yourdevelopment kit. These documents ensure that you have:• Installed the required software.• Determined that the development board functions properly and is connected to your computer.Next step is to install the USB-Blaster driver, if not already done. To install the driver, connect aUSB cable between the DE0-Nano board and a USB port on a computer that is running the QuartusII software.The computer will recognize the new hardware connected to its USB port, but it will be unable toproceed if it does not have the required driver already installed.

If the USB-Blaster driver is notalready installed, the New Hardware Wizard in Figure 6-2 will appear.41Figure 6-2 Found New Hardware WizardThe desired driver is not available on the Windows Update Web site, therefore select “No, not thistime” and click Next. This leads to the window in Figure 6-3.Figure 6-3 The driver is found in a specific location42The driver is available within the Quartus II software. Hence, select “Install from a list or specificlocation” and click Next to get to Figure 6-4.Figure 6-4 Specify the location of the driverNow, select “Search for the best driver in these locations” and click Browse to get to the pop-updialog box in Figure 6-5 Find the desired driver, which is at locationC:\altera\10.1\quartus\drivers\usb-blaster. Click OK and then upon returning to Figure 6-4 clickNext.

At this point the installation will commence, but a dialog box in Figure 6-6 will appearindicating that the driver has not passed the Windows Logo testing. Click Continue Anyway.43Figure 6-5 Browse to find the locationFigure 6-6 There is no need to test the driver44The driver will now be installed as indicated in Figure 6-7. Click Finish and you can start using theDE0-Nano board.Figure 6-7 The driver is installed6.3 W hat You W ill Lear nIn this tutorial you will perform the following tasks:Create a design that causes LEDs on the development board to blink at two distinct rates.

Thisdesign is easy to create and gives you visual feedback that the design works. Of course, you can useyour DE0-Nano board to run other designs as well. For the LED design, you will write Verilog HDLcode for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock source,and add a 2-input multiplexer megafunction. When the design is running on the board, you canpress an input switch to multiplex the counter bits that drive the output LEDs.6.4 Assign T he DeviceBegin this tutorial by creating a new Quartus II project.

A project is a set of files that maintaininformation about your FPGA design. The Quartus II Settings File (.qsf) and Quartus II Project File(.qpf) files are the primary files in a Quartus II project. To compile a design or make pinassignments, you must first create a project. The steps used to create a project are:451. In the Quartus II software, select File > New Project Wizard. The Introduction page opens, asshown in Figure 6-8.Figure 6-8 New Project Wizard introduction2.Click Next.3.

Enter the following information about your project: (Note: File names, project names, anddirectories in the Quartus II software cannot contain spaces.)a. What is the working directory for this project? Enter a directory in which you will store yourQuartus II project files for this design. For example, E:\My_design\my_first_fpga.b.What is the name of this project? Type my_first_fpga.c. What is the name of the top-level design entity for this project? Type my_first_fpga.

SeeFigure 6-9.46Figure 6-9 Project informationd.Click Next.e. In the next dialog box, you will assign a specific FPGA device to the design. Select theEP4CE22F17C6 device, as it is the FPGA on the DE0-Nano, as shown in Figure 6-10.47Figure 6-10 Specify the Device Examplef.Click Finish.4. When prompted, select Yes to create the my_first_fpga project directory.

You just created yourQuartus II FPGA project. Your project is now open in Quartus II, as shown in Figure 6-11.48Figure 6-11 my_first_fpga project6.5 Creating an FPGA designThis section describes how to create an FPGA design. This includes creating the top-level design,adding components (in Verilog HDL and using the megafunctions), adding pins and interconnectingall the components and pins.First, create a top-level module. In this tutorial, you will use schematic entry, via a Block DesignFile (.bdf). Alternatively, you could use Verilog HDL or VHDL for the top-level module. Thefollowing steps describe how to create the top-level schematic.1.

Select File > New > Block Diagram/Schematic File (see Figure 6-12 to create a new file,Block1.bdf, which you will save as the top-level design.49Figure 6-12 New BDF2.Click OK.3.Select File > Save As and enter the following information.• File name: my_first_fpga• Save as type: Block Diagram/Schematic File (*.bdf)4.Click Save. The new design file appears in the Block Editor (see Figure 6-13).50Figure 6-13 Bank BDFAdding a Verilog HDL to the Schematic1.Add HDL code to the blank block diagram by choosing File > New > Verilog HDL File.2.Select Verilog HDL File in the tree and Click OK.3.

Save the newly created file, by selecting File > Save As and entering the following information(see Figure 6-14).• File name: simple_counter.v• Save as type: Verilog HDL File (*.v, *.vlg, *.verilog)51Figure 6-14 Saving the Verilog HDL fileThe resulting empty file is ready for you to enter the Verilog HDL code.4. Type the following Verilog HDL code into the blank simple_counter.v file, as shown in Figure6-15.//It has a single clock input and a 32-bit output portmodule simple_counter (CLOCK_5,counter_out);inputCLOCK_5 ;output [31:0] counter_out;reg[31:0] counter_out;52always @ (posedge CLOCK_5)// on positive clock edgebegincounter_out <= counter_out + 1;// increment counterendendmodule// end of module counterFigure 6-15 The Verilog File of simple_counter.v5.Save the file by choosing File > Save, pressing Ctrl + S, or by clicking the floppy disk icon.6.

Select File > Create/Update > Create Symbol Files for Current File to convert thesimple_counter.v file to a Symbol File (.sym). You will use this Symbol File to add the HDL codeto your schematic.The Quartus II software creates a Symbol File and displays a message (see Figure 6-16).Figure 6-16 Create Symbol File was Successful7.Click OK.8.To add the simple_counter.v symbol to the top-level design, click the my_first_fpga.bdf tab.539.Right click in the blank area of the BDF file, and select Insert > Symbol.10. Double-click the Project directory to expand it.11.

Select the newly created simple_counter symbol by clicking its icon.Figure 6-17 Adding the Symbol to the BDF12.Click OK.13. Move the cursor to the BDF grid; the symbol image moves with the cursor. Click to place thesimple_counter symbol onto the BDF. You can move the block after placing it by simply clickingand dragging it to where you want it and releasing the mouse button to place it. See Figure 6-18.Figure 6-18 Placing the simple_counter symbol5414.Press the Esc key or click an empty place on the schematic grid to cancel placing furtherinstances of this symbol.15.Save your project regularly.Adding a Megafunction to the SchematicMegafunctions, such as the ones available in the LPM, are pre-designed modules that you can use inFPGA designs. These Altera-provided megafunctions are optimized for speed, area, and devicefamily. You can increase efficiency by using a megafunction instead of writing the function yourself.Altera also provides more complex functions, called MegaCore functions, which you can evaluatefor free but require a license file for use in production designs.

This tutorial design uses a PLL clocksource to drive a simple counter. A PLL uses the on-board oscillator (DE0-Nano Board is 50 MHz)to create a constant clock frequency as the input to the counter. To create the clock source, you willadd a pre-built LPM megafunction named ALTPLL.1. Right click in the blank space in the BDF and select Insert > Symbol or click the Add Symbolicon on the toolbar.2. Click the Megawizard Plug-in Manager button. The MegaWizard® Plug-In Manager appears,as shown in Figure 6-19.Figure 6-19 Mega Wizard Plug-In Manager553.Click Next.4.In MegaWizard Plug-In Manager [page 2a], specify the following selections (see Figure 6-20):a.Select I/O > ALTPLL.b.

Under “Which device family will you be using?” select the Cyclone IV E for DE0-Nanodevelopment board.c.Under “Which type of output file do you want to create?” select Verilog HDL.d. Under “What name do you want for the output file?” type pll at the end of the already createddirectory name.e.Click Next.Figure 6-20 MegaWizard Plug-In Manager [page 2a] Selections5. In the MegaWizard Plug-In Manager [page 3 of 14] window, make the following selections(see Figure 6-21).a.Confirm that the currently selected device family option is set to Cyclone IV E.b.For device speed grade choose 6 for DE0-Nano.c.Set the frequency of the inclock0 input 50 MHz.56d.Click Next.Figure 6-21 MegaWizard Plug-In Manager [page 3 of 14] Selections6.

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