DE0_Nano_User_Manual_v1.9 (1162595), страница 6
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Unselect all options on MegaWizard page 4. As you turn them off, pins disappear from the PLLblock’s graphical preview. See Figure 6-22 for an example.57Figure 6-22 MegaWizard Plug-In Manager [page 4 of 14] Selections7.Click Next four times to get to page 8.8.Set the Clock division factor to 10, as shown in Figure 6-23.58Figure 6-23 MegaWizard Plug-In Manager [page 8 of 14] Selections9.Click Next and then click Finish.10.
The wizard displays a summary of the files it creates (see Figure 6-24). Select the pll.bsfoption and click Finish again.59Figure 6-24 Wizard-Created FilesThe Symbol window opens, showing the newly created PLL megafunction,a s shown in Figure6-25.60Figure 6-25 PLL Symbol11. Click OK and place the pll symbol onto the BDF to the left of the simple_counter symbol. Youcan drag and drop the symbols, if you need to rearrange them. See Figure 6-26.Figure 6-26 Place the PLL Symbol12.
Move the mouse so that the cursor (also called the selection tool) is over the pll symbol’s c0output pin. The orthogonal node tool (cross-hair) icon appears.13. Click and drag a bus line from the c0 output to the simple_counter clock input. This action tiesthe pll output to the simple_counter input (see Figure 6-27).61Figure 6-27 Draw a Bus Line connect pll c0 port to simple_counter CLOCK_5 portAdding an Input pin to the SchematicThe following steps describe how to add an input pin to the schematic.1.Right click in the blank area of the BDF and select Insert > Symbol.2.Under Libraries, select quartus/libraries > primitives > pin >input. See Figure 6-283.Click OKIf you need more room to place symbols, you can use the vertical and horizontal scroll bars at theedges of the BDF window to view more drawing space.Figure 6-28 Input pin symbol624.Place the new pin onto the BDF so that it is touching the input to the pll symbol.5.
Use the mouse to click and drag the new input pin to the left; notice that the ports remainconnected as shown in Figure 6-29.Figure 6-29 Connecting the PLL symbol and Input port6. Change the pin name by double-clicking pin_name and typing CLOCK_50 (see Figure 6-30).This name correlates to the oscillator clock that is connected to the FPGA.Adding an Output bus to the SchematicThe following steps describe how to add an output bus to the schematic.1. Using the Orthogonal Bus tool, draw a bus line connected on one side to the simple_counteroutput port, and leave the other end unconnected at about 4 to 8 grid spaces to the right of thesimple_counter.63Figure 6-30 Change the input port name2.Right-click the new output bus line and select Properties.3.
Type counter [31..0] as the bus name (see Figure 6-31). The notation [X ..Y] is the Quartus IImethod for specifying the bus width in BDF schematics, where X is the most significant bit (MSB)and Y is the least significant bit (LSB).4.Click OK. Figure 6-32 shows the BDF.64Figure 6-31 Change the output BUS nameFigure 6-32 Circuit schematic (BDF)Adding a Multiplexer to the SchematicThis design uses a multiplexer to route the simple_counter output to the LED pins on the DE0-Nanodevelopment board.
You will use the MegaWizard Plug-In Manager to add the multiplexer,lpm_mux. The design multiplexes two portions of the counter bus to four LEDs on the DE0-Nanoboard. The following steps describe how to add a multiplexer to the schematic.651.Right click in the blank area of the BDF and select Insert > Symbol.2.Click Megawizard Plug-in Manager.3.Click Next.4.Select Installed Plug-Ins > Gates > LPM_MUX.5.
Select the Cyclone IV E device family, Verilog HDL as the output file type, and name theoutput file counter_bus_mux.v, as shown in Figure 6-33.6.Click Next.Figure 6-33 Selecting lpm_mux7.Under “How many ‘data’ inputs do you want?” select 2 inputs (default).8. Under “How wide should the ‘data’ input and the ‘result’ output buses be?” select 4, as shownin Figure 6-34.66Figure 6-34 lpm_mux settings9.Click Next.10. Click Next.11.
Select the counter_bus_mux.bsf option.12.Click Finish. The Symbol window appears (see Figure 6-35 for an example).67Figure 6-35 lpm_mux Symbol13. Click OK14. Place the counter_bus_mux symbol below the existing symbols on the BDF, as shown inFigure 6-36.Figure 6-36 Place the lpm_mux symbol6815. Add input buses and output pins to the counter_bus_mux symbol as follows:a. Using the Orthogonal Bus tool, draw bus lines from the data1x[3..0] and data0x[3..0] inputports to about 8 to 12 grid spaces to the left of counter_bus_mux.b.
Draw a bus line from the result [3..0] output port to about 6 to 8 grid spaces to the right ofcounter_bus_mux.c.Right-click the bus line connected to data1x[3..0] and select Properties.d. Name the bus counter[26..23], which selects only those counter output bits to connect to thefour bits of the data1x input.Because the input busses to counter_bus_mux have the same names as the output bus fromsimple_counter, (counter[x ..
y]) the Quartus II software knows to connect these busses.e.Click OK.f.Right-click the bus line connected to data0x[3..0] and select Properties.g. Name the bus counter [24..21], which selects only those counter output bits to connect to thefour bits of the data1x input.h.Click OK. Figure 6-37 shows the renamed buses.Figure 6-37 Renamed counter_bus_mux Bus LinesIf you have not done so already, you may want to save your project file before continuing.16.
Right click in the blank area of the BDF and select Insert > Symbol.17. Under Libraries, select quartus/libraries > primitives > pin >output, as shown in Figure 6-38.69Figure 6-38 Choose output pin18. Click OK.19. Place this output pin so that it connects to the counter_bus_mux’s result [3..0] bus output line.20. Rename the output pin as LED [3..0]. (see Figure 6-39).Figure 6-39 Rename the output pin21. Attach an input pin to the multiplexer select line using an input pin:a.Right click in the blank area of the BDF and select Insert > Symbol.b.Under Libraries, double-click quartus/libraries/ > primitives > pin > input.c.Click OK.22.
Place this input pin below counter_bus_mux.23. Connect the input pin to the counter_bus_mux sel pin.24. Rename the input pin as KEY [0] (see Figure 6-40).70Figure 6-40 Adding the KEY [0] Input PinYou have finished adding all required components of the circuit to your design. You can add notesor information to the project as text using the Text tool on the toolbar (indicated with the A symbol).For example, you can add the label “OFF = SLOW, ON = FAST” to the KEY [0] input pin and adda project description, such as “DE0-Nano Tutorial Project.”6.6 Assign the PinsIn this section, you will make pin assignments. Before making pin assignments, perform thefollowing steps:1. Select Processing > Start > Start Analysis & Elaboration in preparation for assigning pinlocations.2.Click OK in the message window that appears after analysis and elaboration completes.To make pin assignments to the KEY [0] and CLOCK_50 input pins and to the LED[3..0] outputpins, perform the following steps:1.
Select Assignments > Pin Planner, which opens the Pin Planner, a spreadsheet-like table ofspecific pin assignments. The Pin Planner shows the design’s six pins. See Figure 6-4171Figure 6-41 Pin Planner Example2. In the Location column next to each of the six node names, add the coordinates (pin numbers)as shown in Table 6-1 for the actual values to use with your DE0-Nano board.Table 6-1 Pin Information SettingPin NameKEY[0]LED[3]LED[2]LED [1]LED [0]CLOCK_50FPGA Pin LocationJ15A11B13A13A15R8Double-click in the Location column for any of the six pins to open a drop-down list and type thelocation shown in the table. Alternatively, you can select the pin from a drop-down list.
For example,if you type F1 and press the Enter key, the Quartus II software fills in the full PIN_F1 locationname for you. The software also keeps track of corresponding FPGA data such as the I/O bank andVREF Group. Each bank has a distinct color, which corresponds to the top-view wire bond drawingin the upper right window, as shown in Figure 6-42.72Figure 6-42 Completed Pin Planning ExampleNow, you are finished creating your Quartus II design!6.7 Create a Default TimeQuest SDC FileTiming settings are critically important for a successful design.
For this tutorial you will create abasic Synopsys Design Constraints File (.sdc) that the Quartus II TimeQuest Timing Analyzer usesduring design compilation. For more complex designs, you will need to consider the timingrequirements more carefully.To create an SDC, perform the following steps:1.Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer.2.Select File > New SDC file. The SDC editor opens.3.Type the following code into the editor:create_clock -period 20.000 -name CLOCK_50derive_pll_clocksderive_clock_uncertainty4.Save this file as my_first_fpga.sdc (see Figure 6-43)73Figure 6-43 Default SDCNaming the SDC with the same name as the top-level file causes the Quartus II software to use thistiming analysis file automatically by default. If you used another name, you would need to add theSDC to the Quartus II assignments file.6.8 Compile Your DesignAfter creating your design you must compile it.
Compilation converts the design into a bitstreamthat can be downloaded into the FPGA. The most important output of compilation is an SRAMObject File (.sof), which you use to program the device. Also, the software generates report filesthat provide information about your circuit as it compiles.Now that you have created a complete Quartus II project and entered all assignments, you cancompile the design.In the Processing menu, select Start Compilation or click the Play button on the toolbar.If you are asked to save changes to your BDF, click Yes.While compiling your design, the Quartus II software provides useful information about thecompilation, as shown in Figure 6-44.74Figure 6-44 Compilation Message for projectWhen compilation is complete, the Quartus II software displays a message.
Click OK to close themessage box.The Quartus II Messages window displays many messages during compilation. It should not displayany critical warnings; it may display a few warnings that indicate that the device timing informationis preliminary or that some parameters on the I/O pins used for the LEDs were not set. The softwareprovides the compilation results in the Compilation Report tab as shown in Figure 6-45.75Figure 6-45 Compilation Report Example6.9 Program the FPGA DeviceAfter compiling and verifying your design you are ready to program the FPGA on the developmentboard.
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