DE0_Nano_User_Manual_v1.9 (1162595), страница 4
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Thevoltage shown is the voltage reading from the separate pins on the extension header. Figure 4-7shows the ADC readings when the ADC tab is chosen.Figure 4-7 ADC Readings324.7 Overall Structure of the DE0-Nano Control PanelThe DE0-Nano Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV EFPGA with software running on the on-chip memory.
The software part is implemented in C code;the hardware part is implemented in Verilog HDL code with SOPC builder. The source code is notavailable on the DE0-Nano System CD.To run the Control Panel, users should make the configuration according to Section 4.1. Figure 4-8depicts the structure of the Control Panel.
Each input/output device is controlled by the Nios IIProcessor instantiated in the FPGA chip. The communication with the PC is done via the USBBlaster link. The Nios II interprets the commands sent from the PC and performs the correspondingactions.Figure 4-8 The block diagram of the DE0-Nano Control Panel33Chapter 5DE0DE0-Nano System BuilderThis chapter describes how users can create a custom design project on the DE0-Nano board byusing DE0-Nano Tool – DE0-Nano System Builder.5.1 IntroductionThe DE0-Nano System Builder is a Windows based software utility, designed to assist users increating a Quartus II project for the DE0-Nano board within minutes.
The generated Quartus IIproject files include:•••••Quartus II Project File (.qpf)Quartus II Setting File (.qsf)Top-Level Design File (.v)Synopsys Design Constraints file (.sdc)Pin Assignment Document (.htm)By providing the above files, DE0-Nano System Builder helps to prevents occurrence of situationsthat are prone to errors when users manually edit the top-level design file or place pin assignments.The common mistakes that users encounter are the following:1.Board damaged for wrong pin/bank voltage assignments.2. Board malfunction caused by wrong device connections or missing pin counts for connectedends.3.Performance degeneration because of improper pin assignments.5.2 General Design FlowThis section will introduce the general design flow to build a project for the DE0-Nano board viathe DE0-Nano System Builder.
The general design flow is illustrated in Figure 5-1.To create a new system using the DE0-Nano System Builder, begin by launching the DE0-NanoSystem Builder software. The software will then prompt you to specify the name of the project youwish to create, as well as the components on the DE0-Nano board you wish to you. Once yourspecification is complete, you can generate the system.34The generated system is described using several files. In particular, there is the project file (.qpf),the top-level Verilog wrapper file (.v) that describes the I/O pins you will use in your design, andthe Quartus II settings file (.qsf) that specifies which pin on the FPGA each I/O in your designshould connect to.
A Synopsys Design Constraints (.sdc) file with timing constraints and an HTMLfile with pin descriptions will be generated as well.To proceed with your design, open the Quartus II CAD software and open your newly-createdproject. You will now be able to implement the logic of your design by describing your design in ahardware description language, and connecting it to I/Os in the top-level wrapper file. Once yourdesign is complete, compile the design using Quartus II, and then use the Quartus II Programmertool to configure the FPGA on the DE0-Nano board, using the JTAG programming mode.Figure 5-1The general design flow of building a design355.3 Using DE0-Nano System BuilderThis section provides the detailed procedures on how the to use the DE0-Nano System Builder.Install and launch the DE0-Nano System BuilderThe DE0-Nano System Builder is located in the directory: "Tools\DE0_NANO_SystemBuilder" onthe DE0-Nano System CD.
Users can copy the whole folder to a host computer without installingthe utility. Launch the DE0-Nano System Builder by executing the DE0_NANO_SystemBuilder.exeon the host computer and the GUI window will appear as shown in Figure 5-2.Figure 5-2The DE0-Nano System Builder windowInput Project NameInput project name as show in Figure 5-3.Project Name: Type in an appropriate name here, it will automatically be assigned as the name ofyour top-level design entity.36Figure 5-3The DE0-Nano Board Type and Project NameSystem ConfigurationUnder System Configuration users are given the flexibility of enabling their choice of includedcomponents on the DE0-Nano as shown in Figure 5-4.
Each component of the DE0-Nano is listedwhere users can enable or disable a component according to their design by simply marking a checkor removing the check in the field provided. If the component is enabled, the DE0-Nano SystemBuilder will automatically generate the associated pin assignments including the pin name, pinlocation, pin direction, and I/O standard.Figure 5-4System Configuration GroupGPIO Expansion37Users can connect GPIO expansion card onto GPIO header located on the DE0-Nano board asshown in Figure 5-5. Select the appropriate daughter card you wish to include in your design fromthe drop-down menu.
The system builder will automatically generate the associated pin assignmentsincluding the pin name, pin location, pin direction, and IO standard.If a customized daughter board is used, users can select “GPIO Default” followed by changing thepin name and pin direction according to the specification of the customized daughter board.Figure 5-5GPIO Expansion GroupThe “Prefix Name” is an optional feature which denotes the prefix pin name of the daughter cardassigned in your design. Users may leave this field empty.Project Setting ManagementThe DE0-Nano System Builder also provides functions to restore default setting, loading a setting,and saving users’ board configuration file shown in Figure 5-6.
Users can save the current boardconfiguration information into a .cfg file and load it to the DE0-Nano System Builder.38Figure 5-6Project SettingsProject GenerationWhen users press the Generate button, the DE0-Nano System Builder will generate thecorresponding Quartus II files and documents as listed in the Table 5-1:Table 5-1The files generated by DE0-Nano System BuilderNo.1Filename<Project name>.vDescriptionTop level Verilog HDL file for Quartus II2<Project name>.qpfQuartus II Project File3<Project name>.qsfQuartus II Setting File4<Project name>.sdcSynopsys Design Constraints file for Quartus II5<Project name>.htmPin Assignment DocumentUsers can use Quartus II software to add custom logic into the project and compile the project togenerate the SRAM Object File (.sof).39Chapter 6Tutorial: Creating an FPGA ProjectThis tutorial provides comprehensive information for understanding how to create a FPGA designand run it on the DE0-Nano development and education board.
The following sections provide aquick overview of the design flow, explaining what is needed to get started, and describe what istaught in this tutorial.6.1 Design FlowFigure 6-1shows a block diagram of the FPGA design flow.The first step in the FPGA design flow starts is design entry. The standard design entry methods areusing schematics or a hardware description language (HDL), such as Verilog HDL or VHDL.
Thedesign entry step is where the designer creates the digital circuit to be implemented inside theFPGA. The flow then proceeds through compilation, simulation, programming, and verification inthe FPGA hardware.Figure 6-1 Design FlowThis tutorial describes all of the steps except for simulation. Although it is not covered in thisdocument, simulation is very important to learn. There are two types of simulation, Functional andTiming Functional simulation allows you to verify that your hardware is performing the desiredfunctionality. Timing (or post place-and-route) simulation verifies that the design meets timing andfunctions appropriately in the device.
Simulation tutorials can be found on the Altera UniversityProgram website at http://university.altera.com.406.2 Before You BeginThis tutorial assumes the following prerequisites■ You have a general understanding of FPGAs. This tutorial does not explain the basic conceptsof programmable logic.■ You are somewhat familiar with digital circuit design and electronic design automation (EDA)tools.■ You have installed the Altera Quartus II 10.1 software on your computer. If you do not have theQuartus II software, you can download it from the Altera web site at www.altera.com/download.■ You have a DE0-Nano Development Board on which you will test your project.
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