DE0_Nano_User_Manual_v1.9 (1162595), страница 2
Текст из файла (страница 2)
For connecting to real-world sensors the DE0-Nano includes aNational Semiconductor 8-channel 12-bit A/D converter, and it also features an Analog Devices13-bit, 3-axis accelerometer device.The DE0-Nano board includes a built-in USB Blaster for FPGA programming, and the board can bepowered either from this USB port or by an external power source. The board includes expansionheaders that can be used to attach various Terasic daughter cards or other devices, such as motorsand actuators. Inputs and outputs include 2 pushbuttons, 8 user LEDs and a set of 4 dip-switches.1.1 FeaturesFigure 1-1 shows a photograph of the DE0-Nano Board.Figure 1-1The DE0-Nano Board5The key features of the board are listed below:• Featured deviceo Altera Cyclone® IV EP4CE22F17C6N FPGAo 153 maximum FPGA I/O pins• Configuration status and set-up elementso On-board USB-Blaster circuit for programmingo Spansion EPCS64• Expansion headero Two 40-pin Headers (GPIOs) provide 72 I/O pins, 5V power pins, two 3.3V power pins andfour ground pins• Memory deviceso 32MB SDRAMo 2Kb I2C EEPROM• General user input/outputo 8 green LEDso 2 debounced pushbuttonso 4-position DIP switch• G-Sensoro ADI ADXL345, 3-axis accelerometer with high resolution (13-bit)• A/D Convertero NS ADC128S022, 8-Channel, 12-bit A/D Convertero 50 Ksps to 200 Ksps• Clock systemo On-board 50MHz clock oscillator• Power Supplyo USB Type mini-AB port (5V)o DC 5V pin for each GPIO header (2 DC 5V pins)o 2-pin external power header (3.6-5.7V)61.2 About the KITThe kit comes with the following contents:• DE0-Nano board• System CD-ROM.• USB CableThe system CD contains technical documents for the DE0-Nano board, which includes componentdatasheets, demonstrations, schematic, and user manual.Figure 1-2 shows the photograph of the DE0-Nano kit contents.Figure 1-2DE0-Nano kit package contents1.3 Getting HelpHere is information of how to get help if you encounter any problem:• Terasic Technologies• Tel: +886-3-575-0880• Email: support@terasic.com• Altera Corporation• Email: university@altera.com7Chapter 2DE0DE0-Nano Board ArchitectureThis chapter describes the architecture of the DE0-Nano board including block diagram andcomponents.2.1 Layout and ComponentsThe picture of the DE0-Nano board is shown in Figure 2-1 and Figure 2-2.
It depicts the layout ofthe board and indicates the locations of the connectors and key components.Figure 2-1The DE0-Nano Board PCB and component diagram (top view)8Figure 2-2 The DE0-Nano Board PCB and component diagram (bottom view)2.2 Block Diagram of the DE0-Nano BoardFigure 2-3 shows the block diagram of the DE0-Nano board.
To provide maximum flexibility forthe user, all connections are made through the Cyclone IV FPGA device. Thus, the user canconfigure the FPGA to implement any system design.Figure 2-3 Block diagram of DE0-Nano Board92.3 Power-up the DE0-Nano BoardThe DE0-Nano board comes with a preloaded configuration bit stream to demonstrate somefeatures of the board. This allows users to see quickly if the board is working properly.
To power-upthe board two options are available which are described below:1. Connect a USB Mini-B cable between a USB (Type A) host port and the board. Forcommunication between the host and the DE0-Nano board, it is necessary to install the Altera USBBlaster driver software.2. Alternatively, users can power-up the DE0-Nano board by supplying 5V to the two DC +5(VCC5) pins of the GPIO headers or supplying (3.6-5.7V) to the 2-pin header.At this point you should observe flashing LEDs on the board.10Chapter 3Using the DE0DE0-Nano BoardThis chapter gives instructions for using the DE0-Nano board and describes in detail its componentsand connectors, along with the required pin assignments.3.1 Configuring the Cyclone IV FPGAThe DE0-Nano board contains a Cyclone IV E FPGA which can be programmed using JTAGprogramming.
This allows users to configure the FPGA with a specified design using Quartus IIsoftware. The programmed design will remain functional on the FPGA as long as the board ispowered on, or until the device is reprogrammed. The configuration information will be lost whenthe power is turned off.To download a configuration bit stream file using JTAG Programming into the Cyclone IV FPGA,perform the following steps:1.Connect a USB Mini-B cable between a host computer and the DE0-Nano.2.
The FPGA can now be programmed through the Quartus II Programmer by selecting aconfiguration bit stream file with the .sof filename extension.Configuring the Spansion EPCS64 deviceThe DE0-Nano board contains a Spansion EPCS64 serial configuration device. This deviceprovides non-volatile storage of the configuration bit-stream, so that the information is retainedeven when the power supply to the DE0-Nano board is turned off. When the board’s power isturned on, the configuration data in the EPCS64 device is automatically loaded into the Cyclone IVE FPGA.The Cyclone IV E device supports in-system programming of a serial configuration device usingthe JTAG interface via the serial flash loader design. The serial flash loader is a bridge design forthe Cyclone IV E device that uses its JTAG interface to access the EPCS .jic file and then uses theAS interface to program the EPCS device.
Figure 3-1 illustrates the programming method whenadopting a serial flash loader solution. Chapter 9 of this document describes how to load a circuit tothe serial configuration device.11Figure 3-1 Programming a serial configuration device with serial flash loader solutionJTAG Chain on DE0-Nano BoardThe JTAG Chain on the DE0-Nano board is connected to a host computer using an on-boardUSB-blaster.
The USB-blaster consists of a USB Mini-B connector, a FTDI USB 2.0 Controller,and an Altera MAX II CPLD.Figure 3-2 illustrates the JTAG configuration setup.Figure 3-2 JTAG Chain3.2 General User Input/OutputPushbuttonsThe DE0-Nano board contains two pushbuttons shown in Figure 3-3. Each pushbutton isdebounced using a Schmitt Trigger circuit, as indicated in Figure 3-4. The two outputs called KEY0,and KEY1 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA.
Eachpushbutton provides a high logic level when it is not pressed, and provides a low logic level whenpressed. Since the pushbuttons are debounced, they are appropriate for using as clock or resetinputs.12Figure 3-3Connections between the push-buttons and Cyclone IV FPGAPushbutton depressedPushbutton releasedBeforeDebouncingSchmitt TriggerDebouncedFigure 3-4Pushbuttons debouncingLEDsThere are 8 green user-controllable LEDs on the DE0-Nano board. The eight LEDs, which arepresented in Figure 3-4, allow users to display status and debugging information.
Each LED isdriven directly by the Cyclone IV E FPGA. Each LED is driven directly by a pin on the Cyclone IVE FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin lowturns it off.13Figure 3-5 Connections between the LEDs and Cyclone IV FPGADIP SwitchThe DE0-Nano board contains a 4 dip switches. A DIP switch provides, to the FPGA, a high logiclevel when it is in the DOWN position, and a low logic level when in the UPPER position.Table 3-1Signal NameKEY[0]KEY[1]Pin Assignments for Push-buttonsFPGA Pin No.PIN_J15PIN_E1DescriptionPush-button[0]Push-button[1]I/O Standard3.3V3.3VTable 3-2 Pin Assignments for LEDsSignal NameLED[0]LED[1]LED[2]LED[3]LED[4]LED[5]LED[6]LED[7]FPGA Pin No.PIN_A15PIN_A13PIN_B13PIN_A11PIN_D1PIN_F3PIN_B1PIN_L3DescriptionLED Green[0]LED Green[1]LED Green[2]LED Green[3]LED Green[4]LED Green[5]LED Green[6]LED Green[7]14I/O Standard3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3VTable 3-3 Pin Assignments for DIP SwitchesSignal NameDIP Switch[0]DIP Switch[1]DIP Switch[2]DIP Switch[3]FPGA Pin No.PIN_M1PIN_T8PIN_B9PIN_M15DescriptionDIP Switch[0]DIP Switch[1]DIP Switch[2]DIP Switch[3]I/O Standard3.3V3.3V3.3V3.3V3.3 SDRAM Memor yThe board features a Synchronous Dynamic Random Access Memory (SDRAM) device providing32MB with a 16-bit data lines connected to the FPGA.
The chip uses 3.3V LVCMOS signalingstandard. All signals are registered on the positive edge of the clock signal, DRAM_CLK.Connections between the FPGA and SDRAM chips are shown in Figure 3-6.Figure 3-6Connections between FPGA and SDRAMTable 3-4 SDRAM Pin AssignmentsSignal NameDRAM_ADDR[0]DRAM_ADDR[1]DRAM_ADDR[2]DRAM_ADDR[3]DRAM_ADDR[4]DRAM_ADDR[5]DRAM_ADDR[6]DRAM_ADDR[7]DRAM_ADDR[8]DRAM_ADDR[9]DRAM_ADDR[10]DRAM_ADDR[11]FPGA Pin No.PIN_P2PIN_N5PIN_N6PIN_M8PIN_P8PIN_T7PIN_N8PIN_T6PIN_R1PIN_P1PIN_N2PIN_N1DescriptionSDRAM Address[0]SDRAM Address[1]SDRAM Address[2]SDRAM Address[3]SDRAM Address[4]SDRAM Address[5]SDRAM Address[6]SDRAM Address[7]SDRAM Address[8]SDRAM Address[9]SDRAM Address[10]SDRAM Address[11]15I/O Standard3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3VDRAM_ADDR[12]DRAM_DQ[0]DRAM_DQ[1]DRAM_DQ[2]DRAM_DQ[3]DRAM_DQ[4]DRAM_DQ[5]DRAM_DQ[6]DRAM_DQ[7]DRAM_DQ[8]DRAM_DQ[9]DRAM_DQ[10]DRAM_DQ[11]DRAM_DQ[12]DRAM_DQ[13]DRAM_DQ[14]DRAM_DQ[15]DRAM_BA[0]DRAM_BA[1]DRAM_DQM[0]DRAM_DQM[1]DRAM_RAS_NDRAM_CAS_NDRAM_CKEDRAM_CLKDRAM_WE_NDRAM_CS_NPIN_L4PIN_G2PIN_G1PIN_L8PIN_K5PIN_K2PIN_J2PIN_J1PIN_R7PIN_T4PIN_T2PIN_T3PIN_R3PIN_R5PIN_P3PIN_N3PIN_K1PIN_M7PIN_M6PIN_R6PIN_T5PIN_L2PIN_L1PIN_L7PIN_R4PIN_C2PIN_P6SDRAM Address[12]SDRAM Data[0]SDRAM Data[1]SDRAM Data[2]SDRAM Data[3]SDRAM Data[4]SDRAM Data[5]SDRAM Data[6]SDRAM Data[7]SDRAM Data[8]SDRAM Data[9]SDRAM Data[10]SDRAM Data[11]SDRAM Data[12]SDRAM Data[13]SDRAM Data[14]SDRAM Data[15]SDRAM Bank Address[0]SDRAM Bank Address[1]SDRAM byte Data Mask[0]SDRAM byte Data Mask[1]SDRAM Row Address StrobeSDRAM Column Address StrobeSDRAM Clock EnableSDRAM ClockSDRAM Write EnableSDRAM Chip Select3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.4 I2C Serial EEPROMThe DE0-Nano contains a 2Kbit Electrically Erasable PROM (EEPROM).
The EEPROM isconfigured through a 2-wire I2C serial interface. The device is organized as one block of 256 x 8-bitmemory. The I2C write and read address are 0xA0 and 0xA1, respectively. Figure 3-7 illustrates itsconnections with the Cyclone IV FPGA.16Figure 3-7Connections between FPGA and EEPROMTable 3-5 Pin Assignments for I2C Serial EEPROMSignal NameI2C_SCLKI2C_SDATFPGA Pin No.PIN_F2PIN_F1DescriptionEEPROM clockEEPROM dataI/O Standard3.3V3.3V3.5 Expansion HeadersThe DE0-Nano board provides two 40-pin expansion headers.
Each header connects directly to 36pins of the Cyclone IV E FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and twoGND pins. Figure 3-8 shows the I/O distribution of the GPIO connectors.17Figure 3-8Pin arrangement of the GPIO expansion headersThe pictures below indicate the pin 1 location of the expansion headers.Figure 3-9Pin1 locations of the GPIO expansion headersTable 3-6 GPIO-0 Pin AssignmentsSignal NameFPGA Pin No.DescriptionGPIO_0_IN0PIN_A8GPIO Connection DATAI/O Standard3.3VGPIO_00PIN_D3GPIO Connection DATA3.3VGPIO_0_IN1PIN_B8GPIO Connection DATA3.3VGPIO_01PIN_C3GPIO Connection DATA3.3V18GPIO_02PIN_A2GPIO Connection DATA3.3VGPIO_03PIN_A3GPIO Connection DATA3.3VGPIO_04PIN_B3GPIO Connection DATA3.3VGPIO_05PIN_B4GPIO Connection DATA3.3VGPIO_06PIN_A4GPIO Connection DATA3.3VGPIO_07PIN_B5GPIO Connection DATA3.3VGPIO_08PIN_A5GPIO Connection DATA3.3VGPIO_09PIN_D5GPIO Connection DATA3.3VGPIO_010PIN_B6GPIO Connection DATA3.3VGPIO_011PIN_A6GPIO Connection DATA3.3VGPIO_012PIN_B7GPIO Connection DATA3.3VGPIO_013PIN_D6GPIO Connection DATA3.3VGPIO_014PIN_A7GPIO Connection DATA3.3VGPIO_015PIN_C6GPIO Connection DATA3.3VGPIO_016PIN_C8GPIO Connection DATA3.3VGPIO_017PIN_E6GPIO Connection DATA3.3VGPIO_018PIN_E7GPIO Connection DATA3.3VGPIO_019PIN_D8GPIO Connection DATA3.3VGPIO_020PIN_E8GPIO Connection DATA3.3VGPIO_021PIN_F8GPIO Connection DATA3.3VGPIO_022PIN_F9GPIO Connection DATA3.3VGPIO_023PIN_E9GPIO Connection DATA3.3VGPIO_024PIN_C9GPIO Connection DATA3.3VGPIO_025PIN_D9GPIO Connection DATA3.3VGPIO_026PIN_E11GPIO Connection DATA3.3VGPIO_027PIN_E10GPIO Connection DATA3.3VGPIO_028PIN_C11GPIO Connection DATA3.3VGPIO_029PIN_B11GPIO Connection DATA3.3VGPIO_030PIN_A12GPIO Connection DATA3.3VGPIO_031PIN_D11GPIO Connection DATA3.3VGPIO_032PIN_D12GPIO Connection DATA3.3VGPIO_033PIN_B12GPIO Connection DATA3.3VTable 3-7 GPIO-1 Pin AssignmentsSignal NameFPGA Pin No.DescriptionGPIO_1_IN0PIN_T9GPIO Connection DATAI/O Standard3.3VGPIO_10PIN_F13GPIO Connection DATA3.3VGPIO_1_IN1PIN_R9GPIO Connection DATA3.3VGPIO_11PIN_T15GPIO Connection DATA3.3VGPIO_12PIN_T14GPIO Connection DATA3.3VGPIO_13PIN_T13GPIO Connection DATA3.3VGPIO_14PIN_R13GPIO Connection DATA3.3VGPIO_15PIN_T12GPIO Connection DATA3.3V19GPIO_16PIN_R12GPIO Connection DATA3.3VGPIO_17PIN_T11GPIO Connection DATA3.3VGPIO_18PIN_T10GPIO Connection DATA3.3VGPIO_19PIN_R11GPIO Connection DATA3.3VGPIO_110PIN_P11GPIO Connection DATA3.3VGPIO_111PIN_R10GPIO Connection DATA3.3VGPIO_112PIN_N12GPIO Connection DATA3.3VGPIO_113PIN_P9GPIO Connection DATA3.3VGPIO_114PIN_N9GPIO Connection DATA3.3VGPIO_115PIN_N11GPIO Connection DATA3.3VGPIO_116PIN_L16GPIO Connection DATA3.3VGPIO_117PIN_K16GPIO Connection DATA3.3VGPIO_118PIN_R16GPIO Connection DATA3.3VGPIO_119PIN_L15GPIO Connection DATA3.3VGPIO_120PIN_P15GPIO Connection DATA3.3VGPIO_121PIN_P16GPIO Connection DATA3.3VGPIO_122PIN_R14GPIO Connection DATA3.3VGPIO_123PIN_N16GPIO Connection DATA3.3VGPIO_124PIN_N15GPIO Connection DATA3.3VGPIO_125PIN_P14GPIO Connection DATA3.3VGPIO_126PIN_L14GPIO Connection DATA3.3VGPIO_127PIN_N14GPIO Connection DATA3.3VGPIO_128PIN_M10GPIO Connection DATA3.3VGPIO_129PIN_L13GPIO Connection DATA3.3VGPIO_130PIN_J16GPIO Connection DATA3.3VGPIO_131PIN_K15GPIO Connection DATA3.3VGPIO_132PIN_J13GPIO Connection DATA3.3VGPIO_133PIN_J14GPIO Connection DATA3.3V3.6 A/D Conver ter and 2x13 HeaderThe DE0-Nano contains an ADC128S022 lower power, eight-channel CMOS 12-bitanalog-to-digital converter.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
