DE0_Nano_User_Manual_v1.9 (1162595), страница 7
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You download the SOF you just created into the FPGA using the USB-Blaster circuitry onthe board. Set up your hardware for programming using the following steps:First, connect the USB cable, which was included in your development kit, between the DE0-Nanoand the host computer. Refer to the getting started user guide for detailed instructions on how toconnect the cables.Refer to the getting started user guide for detailed instructions on how to connect the cables.Program the FPGA using the following steps.1.Select Tools > Programmer. The Programmer window opens, as shown in Figure 6-46.76Figure 6-46 Programmer Window2.Click Hardware Setup.3. If it is not already turned on, turn on the USB-Blaster [USB-0] option under currently selectedhardware, as shown in Figure 6-47.77Figure 6-47 Hardware Setting4.Click Close.5.If the file name in the Programmer does not show my_first_fpga.sof, click Add File.6.Select the my_first_fpga.sof file from the project directory (see Figure 6-48).7.Click the Start button.78Figure 6-48 Downloading CompleteCongratulations, you have created, compiled, and programmed your first FPGA design! Thecompiled SRAM Object File (.sof) is loaded onto the FPGA on the development board and thedesign should be running.6.10 Verify T he HardwareWhen you verify the design in hardware, you observe the runtime behavior of the FPGA hardwaredesign and ensure that it is functioning appropriately.Verify the design by performing the following steps:1.
Observe that the four development board LEDs appear to be advancing slowly in a binary countpattern, which is driven by the simple_counter bits [26..23].The LEDs are active low, therefore, when counting begins all LEDs are turned on (the 0000 state).2. Press and hold KEY [0] on the development board and observe that the LEDs advance morequickly. Pressing this KEY causes the design to multiplex using the faster advancing part of thecounter (bits [24..21]).3.
If other LEDs emit faintness light, select Assignments > Device. Click Device and Options. SeeFigure 6-49.79Figure 6-49 Device and OptionsSelect unused pins. Reserve all unused pins: select the As input tri-stated option. See Figure 6-50.80Figure 6-50 Setting unused pinsClick twice OK.4.
In the Processing menu, choose Start Compilation. After the compile, select Tools >Programmer. Select the my_first_fpga.sof file from the project directory. Click Start. At this timeyou could find the other LEDs are off.81Chapter 7Tutorial: Creating a Nios II ProjectThis tutorial provides comprehensive information that will help you understand how to create amicroprocessor system on your FPGA development board and run software on it. This system willbe based on the Altera Nios II processor.7.1 Required FeaturesThis tutorial requires the Quartus II and Nios II EDS software to be installed. The tutorial waswritten for version 10.1 of those software packages. If you are using a different version, there maybe some difference in the flow.
Also, this tutorial requires the DE0-Nano board.7.2 Creation of Hardware DesignThis section describes the flow of how to create a hardware system including a Nios II processor.1. Launch Quartus II then select File > New Project Wizard, start to create a new project. SeeFigure 7-1and Figure 7-2.82Figure 7-1 Start to Create a New ProjectFigure 7-2 New Project Wizard2. Select a working directory for this project, type project name and top-level entity name as shownin Figure 7-3.
Then click Next, you will see a window as shown in Figure 7-4.83Figure 7-3 Input the working directory, the name of project, top-level design entityFigure 7-4 New Project Wizard: Add Files [page 2 of 5]3. Click Next to skip in Add Files window. In the Family & Device Settings window, we willchoose device family and device settings appropriate for the DE0-Nano board. You should choosesettings the same, as shown in Figure 7-5.
Then click Next to get to the window as shown inFigure 7-6.84Figure 7-5 New Project Wizard: Family & Device Settings [page 3 of 5]4. Click Next and will see a window as shown in Figure 7-7. Figure 7-7 is a summary about thenew project. Click Finish to complete the New Project Wizard. Figure 7-8 show the new project.85Figure 7-6 New Project Wizard: EDA Tool Settings [page 4 of 5]Figure 7-7 New Project Wizard: Summary [page 5 of 5]86Figure 7-8 A New Complete Project5.
Select Tools > SOPC Builder to open SOPC Builder, the Altera system generation tool, asshown in Figure 7-9.Figure 7-9 SOPC Builder Menu87Figure 7-10 Create New SOPC System [0]6. Rename System Name as shown in Figure 7-10 and Figure 7-11. Click OK and your will see awindow as shown in Figure 7-12.Figure 7-11 Create New System [1]88Figure 7-12 Create New System[2]7.
Click the clk_0 name in the Clock Settings table to rename clk_0 to clk_50. Press Enter tocomplete the update, as shown in Figure 7-13.Figure 7-13 Rename Clock Name8. In the left hand-side Component Library tree, select Library > Processors > Nios II Processorand click the Add… button to open the Nios II component wizard, as shown in Figure 7-14 andFigure 7-15.89Figure 7-14 Add NIOS II Processor90Figure 7-15 Nios II Processor9.
Click Finish to return to main window as shown in Figure 7-16.91Figure 7-16 Add Nios II CPU completely10. Select the cpu_0 component and right-click then select rename, after this, you can updatecpu_0 to cpu, as shown in Figure 7-17 and Figure 7-18.92Figure 7-17 Rename the CPU (1)Figure 7-18 Rename the CPU (2)9311. Add a second component by selecting Library > Interface Protocols > Serial > JTAG UARTand clicking the Add… button, as shown in Figure 7-19 and Figure 7-20.Figure 7-19 Add the JTAG UART component94Figure 7-20 JTAG UART’s add wizard12. We are going to use the default settings for this component, so click Finish to close the wizardand return to the window as shown in Figure 7-21.95Figure 7-21 JTAG UART13.
Select the jtag_uart_0 component and rename it to jtag_uart as shown in Figure 7-22.96Figure 7-22 Rename JTAG UART15. Add the Library > Memories and Memory Controllers > On-Chip > On-Chip Memory(RAM or ROM) component to system, as shown in Figure 7-23 and Figure 7-24.97Figure 7-23 Add On-Chip Memory98Figure 7-24 On-Chip Memory Box16.
Modify Total memory size setting to 26000 as shown in Figure 7-25. Click Finish to return tothe window as in Figure 7-26.99Figure 7-25 Update Total memory size100Figure 7-26 Add On-Chip memory17. Rename onchip_memory2_0 to onchip_memory2 as shown in Figure 7-27.Figure 7-27 Rename On-Chip memory18. Right click on the cpu component table and select Edit… from the list. Update the Reset Vectorand Exception Vector as shown in Figure 7-28. Then, click Finish to return to the window asshown Figure 7-29.101Figure 7-28 Update CPU settings102Figure 7-29 Updated CPU settings19. Add the Library > Peripherals > Microcontroller Peripherals >PIO (Parallel I/O)component to the system, as shown in Figure 7-30 and Figure 7-31.103Figure 7-30 Add PIO104Figure 7-31 Add PIO20.
Click Finish to use the default settings for this component. This closes the PIO wizard andreturns to the window shown in Figure 7-32.105Figure 7-32 PIO21. Rename pio_0 to pio_led as shown in Figure 7-33.Figure 7-33 Rename PIO10622. Select System > Auto-Assign Base Addresses as shown in Figure 7-34. Then, select File >Refresh System.
After that you will find that there is no error in the message window as shown inFigure 7-35.Figure 7-34 Auto-Assign Base AddressesFigure 7-35 No errors or warnings10723. Click the Generate button, which will pop up a window, as shown in Figure 7-36. Click Save,which bring up the window in Figure 7-37. Input the name, DE0_NANO_SOPC, and click thesave button. The compilation will automatically start. If there are no errors in the generation, thewindow will show a message of success, as shown in Figure 7-38.Figure 7-36 Generate SOPCFigure 7-37 Generate SOPC108Figure 7-38 SOPC Builder generation successful24.
Click Exit to exit the SOPC Builder and return to the window as shown in Figure 7-39.Figure 7-39 Return to Quartus II after exiting SOPC Builder10925. Create a new Verilog HDL file, by selecting File > New, Verilog HDL File and click OK, asshown in Figure 7-40 and Figure 7-41.Figure 7-40 New Verilog fileFigure 7-41 New Verilog File11033. Figure 7-42 show a blank Verilog file.Figure 7-42 A blank verilog file34. Type the following Verilog into the blank file, as shown in Figure 7-43. The moduleDE0_NANO_SOPC is the system created by SOPC Builder and its Verilog can be found in theDE0_NANO_SOPC.v file, as shown in111Figure 7-44 and Figure 7-45.module myfirst_niosii(CLOCK_50,LED);inputCLOCK_50;output [7:0]LED;DE0_NANO_SOPC DE0_NANO_SOPC_inst(.clk_50(CLOCK_50),.out_port_from_the_pio_led (LED),.reset_n(1'b1));endmodule112Figure 7-43 Input verilog TextFigure 7-44 Open DE0_NANO_SOPC.v113Figure 7-45 DE0_NANO_SOPC module35.
Save the newly created Verilog file as myfirst_niosii.v, as shown in Figure 7-46.Figure 7-46 Save the Verilog file11436. Compile the project, by selecting Processing > Start Compilation, as shown in Figure 7-47.Figure 7-48 shows the compilation process.Figure 7-47 Start CompilationFigure 7-48 Execute Compile11537.
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