DE0_Nano_User_Manual_v1.9 (1162595), страница 10
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To terminate the process, press KEY0 or KEY1 on theDE0-Nano board. Upon exiting the demo, the selection menu will be displayed.• Input “2” to start EEPROM Content Dump demo. The demo displays the values in the first 16bytes of the EEPROM. The demo automatically exists, and returns to the selection menu.• Input “3” to start EPCS demo. The demo displays the memory size of EPCS. The demoautomatically exists, and returns to the selection menu.1418.5 G-SensorThis demonstration illustrates how to use the digital accelerometer on the DE0-Nano board to measurethe static acceleration of gravity in tilt-sensing applications.
As the board is tilted from left to right andright to left, the digital accelerometer detects the tilting movement and displays it on the LEDs.Figure 8-13 DE0-Nano on level surfaceDesign ConceptThis section describes the design concepts for this demo. Figure 8-14 shows the block diagram.Figure 8-14 G-Sensor block diagram142In this demo, the accelerometer is controlled through a 3-wire SPI.
Before reading any data from theaccelerometer, the controller sets 1 on the SPI bit in the Register 0x31 – DATA_FORMAT register.The 3-wire SPI Controller block reads the digital accelerometer X-axis value, to determine the tiltof the board. The LEDs are lit up as if they were a bubble, floating to the top of the board.Demonstration Source Code• Project directory: DE0_NANO_GSensor• Bit stream used: DE0_NANO_G_Sensor.sofDemonstration Batch FileDemo Batch File Folder: DE0_NANO_GSensor\demo_batchThe demo batch file includes the following files:• FPGA Configure File: DE0_NANO_G_Sensor.sofDemonstration Setup• Make sure Quartus II is installed on your PC.• Connect USB cable to the DE0-Nano board and install the USB Blaster driver if necessary.• Execute the demo batch file “test.bat” under the batch file folder,DE0_NANO_GSensor\demo_batch.
This will load the demo into the FPGA.• Tilt the DE0-Nano board from side to side and observe the result on the LEDs.8.6 SDRAM Test by Nios IIMany applications use SDRAM to provide temporary storage. In this demonstration hardware andsoftware designs are provided to illustrate how to perform memory access in QSYS. We describehow the Altera’s SDRAM Controller IP is used to access a SDRAM, and how the Nios II processoris used to read and write the SDRAM for hardware verification.
The SDRAM controller handles thecomplex aspects of using SDRAM by initializing the memory devices, managing SDRAM banks,and keeping the devices refreshed at appropriate intervals.System Block DiagramFigure 8-15 shows the system block diagram of this demonstration. The system requires a 50 MHzclock provided from the board.
The SDRAM controller is configured as a 32MB controller. Theworking frequency of the SDRAM controller is 100MHz, and the Nios II program is running in theSDRAM.143Figure 8-15 Block diagram of the SDRAM Basic DemonstrationThe system flow is controlled by a Nios II program. First, the Nios II program writes test patternsinto the SDRAM. Then, it calls Nios II system function, alt_dcache_flush_all, to make sure all datahas been written to SDRAM. Finally, it reads data from SDRAM for data verification. The programwill show progress in JTAG-Terminal when writing/reading data to/from the SDRAM. Whenverification process is completed, the result is displayed in the JTAG-Terminal.Design Tools••Quartus II 13.0 SP1Nios II Eclipse 13.0 SP1Demonstration Source Code••Quartus Project directory: DE0_NANO_SDRAM_Nios_TestNios II Eclipse: DE0_NANO_SDRAM_Nios_Test \SoftwareNios II Project Compilation•Before you attempt to compile the reference design under Nios II Eclipse, make sure the projectis cleaned first by clicking ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.144Demonstration Batch FileDemo Batch File Folder: DE0_NANO_SDRAM_Nios_Test \demo_batchThe demo batch file includes following files:•••Batch File for USB-Blaster : DE0_NANO_SDRAM_Nios_Test.bat,DE0_NANO_SDRAM_Nios_Test.shFPGA Configure File : DE0_NANO_SDRAM_Nios_Test.sofNios II Program: DE0_NANO_SDRAM_Nios_Test.elfDemonstration Setup•••••Make sure Quartus II and Nios II are installed on your PC.Connect a USB cable to the DE0-Nano board and install USB Blaster driver if necessary.Execute the demo batch file “ DE0_NANO_SDRAM_Nios_Test .bat” under the batch filefolder, DE0_NANO_SDRAM_Nios_Test \demo_batchAfter Nios II program is downloaded and executed successfully, a prompt message will bedisplayed in nios2-terminal.Press KEY1~KEY0 of the DE0-Nano board to start SDRAM verify process.
Press KEY0 forcontinued test.The program will display progressing and result information, as shown in Figure 8-16.Figure 8-16 Display Progress and Result Information for the SDRAM Demonstration145Chapter 9Appendix9.1 Programming the Serial Configuration DeviceThis section describes how to program the serial configuration device with Serial Flash Loader(SFL) function via the JTAG interface.
User can program serial configuration devices with a JTAGindirect configuration (.jic) file. To generate JIC programming files with the Quartus II software,users need to generate a user-specified SRAM object file (.sof) of the circuit they wish to put in theserial configuration device.
Next, users need to convert the SOF to a JIC file. To convert a SOF to aJIC file in Quartus II software, follow these steps:Convert SOF to JIC1.Select File > Convert Programming Files…2.In the Convert Programming Files dialog box, set the Programming file type field to JTAGIndirect Configuration File (.jic).3.In the Configuration device field, specify the targeted serial configuration device, EPCS64.4.In the File name field, browse to the target directory and specify an output file name.5.Highlight the SOF Data row in the table, as shown in Figure 9-1.6.Click Add File.7.Select the SOF that you want to convert to a JIC file.8.Click Open.1469.Highlight the Flash Loader and click Add Device, as shown in Figure 9-2.10. Click OK. The Select Devices page displays.Figure 9-1 Convert Programming Files Dialog Box147Figure 9-2 Highlight Flash Loader11.
Select the targeted FPGA, Cyclone IV E EP4CE22, as shown in Figure 9-3.12. Click OK. The Convert Programming Files page displays, should look like Figure 9-4.13. Select the .sof file, and Click the Properties. Select Compression, click OK, as shown inFigure 9-5.14. Click Generate.148Figure 9-3 Select Devices Page149Figure 9-4 Convert Programming Files Page150Figure 9-5 Compression the sof fileWrite JIC File into Serial Configuration DeviceTo program the serial configuration device with the JIC file that you just created, add the file to theQuartus II Programmer window and follow the steps:1.When the SOF-to-JIC file conversion is complete, add the JIC file to the Quartus IIProgrammer window:i. Select Tools > Programmer.
The Chain1.cdf window displays.ii. Click Add File. From the Select Programming File page, browse to the JIC file.iii. Click Open.1512.Program the serial configuration device by checking the corresponding Program/Configurebox, a Factory default SFL image will be load (See Figure 9-6).Figure 9-6 Quartus II programmer window with one JIC file3.Click Start to program serial configuration device.Erase the Serial Configuration DeviceTo erase the existed file in the serial configuration device, follow the steps listed below:1.Select Tools > Programmer. The Chain1.cdf window displays.2.Click Add File. From the Select Programming File page, browse to a JIC file.3.Click Open.4.Erase the serial configuration device by checking the corresponding Erase box, a Factory152default SFL image will be load (See Figure 9-7).Figure 9-7 Erasing setting in Quartus II programmer window5.Click Start to erase the serial configuration device.1539.2 EPCS Programming via nios-2-flash-programmerBefore programming the EPCS via nios-2-flash-programmer, users must add an EPCS patch filenios-flash-override.txt into the Nios II EDS folder.
The patch file is available in the folderDemonstation\EPCS_Patch of DE0-Nano System CD. Please copy this file to the folder[QuartusInstalledFolder]\nios2eds\bin (e.g. C:\altera\11.1\nios2eds\bin)If the patch file is not included into the Nios II EDS folder, an error will occur as shown in Figure9-8.Figure 9-8 EPCS Message9.3 Revision Histor yVersionV1.0V1.3V1.4V1.5V1.6V1.7V1.8Change LogInitial Version (Preliminary)Add Table 3-1,3-2 and 3-3Modified Digital Accelerometer Description on page 31Modified ADC description on page 32Corrected Digital Accelerometer Schematic on page 23Modified Altera EPCS16 to be Spansion EPCS64Add SDRAM test section9.4 Copyright StatementCopyright © 2012 Terasic Technologies.
All rights reserved.Always visit the DE0-Nano webpage for new applications.We will continue providing interesting examples and labs on our DE0-Nano webpage. Please visitwww.altera.com or DE0-Nano.terasic.com for more information.154.
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