11ETD (1086184), страница 19
Текст из файла (страница 19)
The result of these two dividers in series is the 16X receiver baud rate clock. TheSCR[2:0] bits are not affected by reset and can be changed at any time, although theyshould not be changed when any SCI transfer is in progress.Figure 7-3 and Figure 7-4 illustrate the SCI baud rate timing chain. The prescaler select bits determine the highest baud rate. The rate select bits determine additional divide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clockis the result of dividing the RT clock by 16.MOTOROLA7-10SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATAEXTALXTALINTERNAL BUS CLOCK (PH2)OSCILLATORANDCLOCK GENERATOR(÷4)÷3÷4÷13SCP[1:0]0:0E0:11:01:1ASSCR[2:0]0 :0:0÷20 :0:1÷20 :1:0÷20 :1:17÷16÷21 :0:0÷21 :0:1÷21 :1:0÷21 :1:1SCITRANSMITBAUD RATE(1X)SCIRECEIVEBAUD RATE(16X)SCI BAUD GENERATORFigure 7-3 SCI Baud Rate Generator Block DiagramM68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-11EXTALXTALINTERNAL BUS CLOCK (PH2)OSCILLATORANDCLOCK GENERATOR(÷4)÷3÷4÷13÷ 39SCP[2:0] *0 :0:0E0 :0:10 :1:00:1:11 :0:0ASSCR[2:0]0 :0:07÷20 :0:1÷20 :1:0÷20 :1:1÷16÷21 :0:0÷21 :0:1÷21 :1:0÷21 :1:1SCITRANSMITBAUD RATE(1X)SCIRECEIVEBAUD RATE(16X)* SCP2 IS PRESENT ONLY ON MC68HC(7)11E20.SCI BAUD GENERATOR /39Figure 7-4 MC68HC(7)11E20 SCI Baud Rate Generator Block Diagram7.7 Status Flags and InterruptsThe SCI transmitter has two status flags.
These status flags can be read by software(polled) to tell when the corresponding condition exists. Alternatively, a local interruptenable bit can be set to enable each of these status conditions to generate interruptrequests when the corresponding condition is present. Status flags are automaticallyset by hardware logic conditions, but must be cleared by software, which provides aninterlock mechanism that enables logic to know when software has noticed the statusindication. The software clearing sequence for these flags is automatic — functionsthat are normally performed in response to the status flags also satisfy the conditionsof the clearing sequence.MOTOROLA7-12SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATATDRE and TC flags are normally set when the transmitter is first enabled (TE set toone).
The TDRE flag indicates there is room in the transmit queue to store anotherdata character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIEis zero, TDRE must be polled. When TIE and TDRE are one, an interrupt is requested.The TC flag indicates the transmitter has completed the queue. The TCIE bit is the local interrupt mask for TC. When TCIE is zero, TC must be polled when TCIE is oneand TC is one, an interrupt is requested.Writing a zero to TE requests that the transmitter stop when it can. The transmittercompletes any transmission in progress before actually shutting down. Only an MCUreset can cause the transmitter to stop and shut down immediately.
If TE is written tozero when the transmitter is already idle, the pin reverts to its general-purpose I/Ofunction (synchronized to the bit-rate clock). If anything is being transmitted when TEis written to zero, that character is completed before the pin reverts to general-purposeI/O, but any other characters waiting in the transmit queue are lost. The TC and TDREflags are set at the completion of this last character, even though TE has been disabled.7.7.1 Receiver FlagsThe SCI receiver has five status flags, three of which can generate interrupt requests.The status flags are set by the SCI logic in response to specific conditions in the receiver.
These flags can be read (polled) at any time by software. Refer to Figure 7-5,which shows SCI interrupt arbitration.When an overrun takes place, the new character is lost, and the character that was inits way in the parallel RDR is undisturbed. RDRF is set when a character has beenreceived and transferred into the parallel RDR. The OR flag is set instead of RDRF ifoverrun occurs.
A new character is ready to be transferred into RDR before a previouscharacter is read from RDR.The NF and FE flags provide additional information about the character in the RDR,but do not generate interrupt requests.The last receiver status flag and interrupt source come from the IDLE flag. The RxDline is idle if it has constantly been at logic one for a full character time. The IDLE flagis set only after the RxD line has been busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle.M68HC11 E SERIESTECHNICAL DATASERIAL COMMUNICATIONS INTERFACEMOTOROLA7-137BEGINFLAGRDRF = 1?YNOR = 1?Y7YTIE = 1?RE = 1?YTE = 1?YNYTCIE = 1?NIDLE = 1?YNNNTC = 1?YNNTDRE = 1?RIE = 1?YNYNYILIE = 1?NRE = 1?YNNOVALID SCI REQUESTVALID SCI REQUESTINT SOURCE RESFigure 7-5 Interrupt Source Resolution Within SCIMOTOROLA7-14SERIAL COMMUNICATIONS INTERFACEM68HC11 E SERIESTECHNICAL DATASECTION 8 SERIAL PERIPHERAL INTERFACEThe serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU to communicate synchronously with peripheral devices, suchas transistor-transistor logic (TTL) shift registers, liquid crystal (LCD) display drivers,analog-to-digital converter subsystems, and other microprocessors.
The SPI is alsocapable of inter-processor communication in a multiple master system. The SPI system can be configured as either a master or a slave device. When configured as amaster, data transfer rates can be as high as one-half the E clock rate (1.5 Mbits persecond for a 3-MHz bus frequency). When configured as a slave, data transfers canbe as fast as the E clock rate (3 Mbits per second for a 3-MHz bus frequency).8.1 Functional DescriptionThe central element in the SPI system is the block containing the shift register and theread data buffer.
The system is single buffered in the transmit direction and doublebuffered in the receive direction. This means that new data for transmission cannot bewritten to the shifter until the previous transfer is complete; however, received data istransferred into a parallel read data buffer so the shifter is free to accept a second serial character.
As long as the first character is read out of the read data buffer beforethe next serial character is ready to be transferred, no overrun condition occurs. A single MCU register address is used for reading data from the read data buffer and forwriting data to the shifter.The SPI status block represents the SPI status functions (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). TheSPI control block represents those functions that control the SPI system through theserial peripheral control register (SPCR).Refer to Figure 8-1, which shows the SPI block diagram.M68HC11 E SERIESTECHNICAL DATASERIAL PERIPHERAL INTERFACEMOTOROLA8-18÷2MSBDIVIDER÷4 ÷16 ÷32LSB8/16-BIT SHIFT REGISTERSMMISOPD2MSMOSIPD3READ DATA BUFFERCLOCKSPI CLOCK (MASTER)SCLOCKLOGICSCKPD4MSPR0SSPD5MSTRSPEDWOMSPR1SELECTPIN CONTROL LOGICINTERNALMCU CLOCK8MSTRSPESPR1SPR0MSTRCPOLCPHASPIESPEDWOMMODFSPIFWCOLSPI CONTROL8SPI STATUS REGISTERSPI CONTROL REGISTER8SPI INTERRUPTREQUEST8INTERNALDATA BUSSPI BLOCK 2SPRFigure 8-1 SPI Block Diagram8.2 SPI Transfer FormatsDuring an SPI transfer, data is simultaneously transmitted and received.
A serial clockline synchronizes shifting and sampling of the information on the two serial data lines.A slave select line allows individual selection of a slave SPI device; slave devices thatare not selected do not interfere with SPI bus activities. On a master SPI device, theselect line can optionally be used to indicate a multiple master bus contention. Referto Figure 8-2.MOTOROLA8-2SERIAL PERIPHERAL INTERFACEM68HC11 E SERIESTECHNICAL DATASCK CYCLE #12345678SCK (CPOL = 0)SCK (CPOL = 1)SAMPLE INPUTMSB(CPHA = 0) DATA OUT654321LSBSAMPLE INPUTMSB(CPHA = 1) DATA OUT654321LSBSS (TO SLAVE)SLAVE CPHA=1 TRANSFER IN PROGRESS3MASTER TRANSFER IN PROGRESS214SLAVE CPHA=0 TRANSFER IN PROGRESS51.
SS ASSERTED2. MASTER WRITES TO SPDR3. FIRST SCK EDGE4. SPIF SET5. SS NEGATEDSPI TRANSFER FORMAT 1Figure 8-2 SPI Transfer Format8.2.1 Clock Phase and Polarity ControlsSoftware can select one of four combinations of serial clock phase and polarity usingtwo bits in the SPI control register (SPCR). The clock polarity is specified by the CPOLcontrol bit, which selects an active high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two different transfer formats. The clock phase and polarity should be identical for the masterSPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements.When CPHA equals zero, the SS line must be negated and reasserted between eachsuccessive serial byte.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
