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Interrupt latencyM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-95varies according to the number of cycles required to complete the current instruction.When the CPU begins to service an interrupt, the contents of the CPU registers arepushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts.
The interrupt vector for the highest priority pending source is fetched, and execution continuesat the address specified by the vector. At the end of the interrupt service routine, thereturn from interrupt instruction is executed and the saved registers are pulled from thestack in reverse order so that normal program execution can resume. Refer to SECTION 3 CENTRAL PROCESSING UNIT for further information.Table 5-5 Stacking Order on Entry to Interrupts5Memory LocationCPU RegistersSPPCLSP – 1PCHSP – 2IYLSP – 3IYHSP – 4IXLSP – 5IXHSP – 6ACCASP – 7ACCBSP – 8CCR5.4.2 Non-Maskable Interrupt Request (XIRQ)Non-maskable interrupts are useful because they can always interrupt CPU operations. The most common use for such an interrupt is for serious system problems, suchas program runaway or power failure.
The XIRQ input is an updated version of the NMI(nonmaskable interrupt) input of earlier MCUs.Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable interruptsand XIRQ. After minimum system initialization, software can clear the X bit by a TAPinstruction, enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus,an XIRQ interrupt is a non-maskable interrupt. Because the operation of the I-bit-related interrupt structure has no effect on the X bit, the internal XIRQ pin remains unmasked. In the interrupt priority logic, the XIRQ interrupt has a higher priority than anysource that is maskable by the I bit. All I-bit-related interrupts operate normally withtheir own priority relationship.When an I-bit-related interrupt occurs, the I bit is automatically set by hardware afterstacking the CCR byte.
The X bit is not affected. When an X-bit-related interrupt occurs, both the X and I bits are automatically set by hardware after stacking the CCR.A return from interrupt instruction restores the X and I bits to their pre-interrupt requeststate.5.4.3 Illegal Opcode TrapBecause not all possible opcodes or opcode sequences are defined, the MCU includes an illegal opcode detection circuit, which generates an interrupt request. WhenMOTOROLA5-10RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATAan illegal opcode is detected and the interrupt is recognized, the current value of theprogram counter is stacked. After interrupt service is complete, reinitialize the stackpointer so repeated execution of illegal opcodes does not cause stack underflow.
Leftuninitialized, the illegal opcode vector can point to a memory location that contains anillegal opcode. This condition causes an infinite loop that causes stack underflow. Thestack grows until the system crashes.The illegal opcode trap mechanism works for all unimplemented opcodes on all fouropcode map pages. The address stacked as the return address for the illegal opcodeinterrupt is the address of the first byte of the illegal opcode. Otherwise, it would bealmost impossible to determine whether the illegal opcode had been one or two bytes.The stacked return address can be used as a pointer to the illegal opcode so the illegalopcode service routine can evaluate the offending opcode.5.4.4 Software InterruptSWI is an instruction, and thus cannot be interrupted until complete.
SWI is not inhibited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, oruntil user software clears the I bit in the CCR.5.4.5 Maskable InterruptsThe maskable interrupt structure of the MCU can be extended to include additional external interrupt sources through the IRQ pin.
The default configuration of this pin is alow-level sensitive wired-OR network. When an event triggers an interrupt, a softwareaccessible interrupt flag is set. When enabled, this flag causes a constant request forinterrupt service. After the flag is cleared, the service request is released.5.4.6 Reset and Interrupt ProcessingFigure 5-1 and Figure 5-2 illustrate the reset and interrupt process. Figure 5-1 illustrates how the CPU begins from a reset and how interrupt detection relates to normalopcode fetches. Figure 5-2 is an expansion of a block in Figure 5-1 and illustrates interrupt priorities. Figure 5-3 shows the resolution of interrupt sources within the SCIsubsystem.M68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-115HIGHESTPRIORITYPOWER-ON RESET(POR)DELAY 4064 E CYCLESEXTERNAL RESETCLOCK MONITOR FAIL(WITH CME = 1)LOWESTPRIORITYCOP WATCHDOGTIMEOUT(WITH NOCOP = 0)5LOAD PROGRAM COUNTERWITH CONTENTS OF$FFFE, $FFFF(VECTOR FETCH)LOAD PROGRAM COUNTERWITH CONTENTS OF$FFFC, $FFFD(VECTOR FETCH)LOAD PROGRAM COUNTERWITH CONTENTS OF$FFFA, $FFFB(VECTOR FETCH)SET BITS S, I, AND XRESET MCUHARDWARE1ABEGIN INSTRUCTIONSEQUENCEYBIT X INCCR = 1?NXIRQPIN LOW?YN2ASTACK CPUREGISTERSSET BITS I AND XFETCH VECTOR$FFF4, $FFF5FLOW OUT OF RESET P1Figure 5-1 Processing Flow out of Reset (1 of 2)MOTOROLA5-12RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATA2AYBIT I INCCR = 1?NANY I-BITINTERRUPTPENDING?YSTACK CPUREGISTERSNFETCH OPCODEYSTACK CPUREGISTERSILLEGALOPCODE?SET BIT I IN CCRNFETCH VECTOR$FFF8, $FFF9WAIYINSTRUCTION?5STACK CPUREGISTERSNYSTACK CPUREGISTERSSWIINSTRUCTION?NNSET BIT I IN CCRFETCH VECTOR$FFF6, $FFF7YRESTORE CPUREGISTERSFROM STACKRTIINSTRUCTION?NEXECUTE THISINSTRUCTIONANYINTERRUPTPENDING?YSET BIT I IN CCRRESOLVE INTERRUPTPRIORITY AND FETCHVECTOR FOR HIGHESTPENDING SOURCESEE FIGURE 5Ð21AFLOW OUT OF RESET P2Figure 5-1 Processing Flow out of Reset (2 of 2)M68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-13BEGINX BITIN CCRSET ?YESNOXIRQ PINLOW ?YESSET X BIT IN CCRFETCH VECTOR$FFF4, FFF5NOHIGHESTPRIORITYINTERRUPT?NOIRQ ?YESFETCH VECTORYESFETCH VECTOR$FFF2, FFF3NO5RTII = 1 ?YESNOREAL-TIMEINTERRUPT?YESFETCH VECTOR$FFF0, FFF1YESFETCH VECTOR$FFEE, FFEFYESFETCH VECTOR$FFEC, FFEDYESFETCH VECTOR$FFEA, FFEBYESFETCH VECTOR$FFE8, FFE9NOYESIC1I = 1 ?NOTIMERIC1F ?NOYESIC2I = 1 ?NOTIMERIC2F ?NOYESIC3I = 1 ?NOTIMERIC3F ?NOYESOC1I = 1 ?NOTIMEROC1F ?NO2A2BINT PRIORITY RES P1Figure 5-2 Interrupt Priority Resolution (1 of 2)MOTOROLA5-14RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATA2A2BYOC2I = 1?YYYYTOI = 1?YYYFETCH VECTOR$FFE2, $FFE3FLAGOC5F = 1?YFETCH VECTOR$FFE0, $FFE1YFETCH VECTOR$FFDE, $FFDFYFETCH VECTOR$FFDC, $FFDDYFETCH VECTOR$FFDA, $FFDBYFETCH VECTOR$FFD8, $FFD95FLAGTOF = 1?FLAGPAOVF = 1FLAGPAIF = 1?FLAGSSPIF = 1? ORMODF = 1?NNNYNNSCIINTERRUPT?SEE FIGURE5Ð3FLAGOC4F = 1?NNSPIE = 1?FETCH VECTOR$FFE4, $FFE5NNPAII = 1?YNNPAOVI = 1?FLAGOC3F = 1NNOC5I = 1?FETCH VECTOR$FFE6, $FFE7NNOC4I = 1?YNNOC3I = 1?FLAGOC2F = 1?YFETCH VECTOR$FFD6, $FFD7FETCH VECTOR$FFF2, $FFF3ENDINT PRI RES P2Figure 5-2 Interrupt PriorityResolution (2 of 2)M68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-15BEGINFLAGRDRF = 1?YNOR = 1?YY5TIE = 1?RE = 1?YTE = 1?YNYTCIE = 1?NIDLE = 1?YNNNTC = 1?YNNTDRE = 1?RIE = 1?YNYYILIE = 1?NNRE = 1?YNNOVALID SCI REQUESTVALID SCI REQUESTINT SOURCE RESFigure 5-3 Interrupt Source Resolution Within SCI5.5 Low Power OperationBoth STOP and WAIT suspend CPU operation until a reset or interrupt occurs.
TheWAIT condition suspends processing and reduces power consumption to an intermediate level. The STOP condition turns off all on-chip clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire RAM array.5.5.1 WAITThe WAI opcode places the MCU in the WAIT condition, during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ, an XIRQ, or any of the internally generatedinterrupts, such as the timer or serial interrupts. The on-chip crystal oscillator remainsactive throughout the WAIT standby period.MOTOROLA5-16RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATAThe reduction of power in the WAIT condition depends on how many internal clock signals driving on-chip peripheral functions can be shut down. The CPU is always shutdown during WAIT.
While in the wait state, the address/data bus repeatedly runs readcycles to the address where the CCR contents were stacked. The MCU leaves the waitstate when it senses any interrupt that has not been masked.The free-running timer system is shut down only if the I bit is set to one and the COPsystem is disabled by NOCOP being set to one. Several other systems can also be ina reduced power consumption state depending on the state of software- controlledconfiguration control bits. Power consumption by the analog-to-digital (A/D) converteris not affected significantly by the WAIT condition. However, the A/D converter currentcan be eliminated by writing the ADPU bit to zero. The SPI system is enabled or disabled by the SPE control bit.
The SCI transmitter is enabled or disabled by the TE bit,and the SCI receiver is enabled or disabled by the RE bit. Therefore the power consumption in WAIT is dependent on the particular application.5.5.2 STOPExecuting the STOP instruction while the S bit in the CCR is equal to zero places theMCU in the STOP condition. If the S bit is not zero, the STOP opcode is treated as ano-op (NOP). The STOP condition offers minimum power consumption because allclocks, including the crystal oscillator, are stopped while in this mode. To exit STOPand resume normal processing, a logic low level must be applied to one of the externalinterrupts (IRQ or XIRQ) or to the RESET pin.
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