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A pending edge-triggered IRQ can alsobring the CPU out of STOP.Because all clocks are stopped in this mode, all internal peripheral functions also stop.The data in the internal RAM is retained as long as VDD power is maintained. The CPUstate and I/O pin levels are static and are unchanged by STOP.
Therefore, when aninterrupt comes to restart the system, the MCU resumes processing as if there wereno interruption. If reset is used to restart the system a normal reset sequence resultsin which all I/O pins and functions are also restored to their initial states.To use the IRQ pin as a means of recovering from STOP, the I bit in the CCR must beclear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from STOPregardless of the state of the X bit in the CCR, although the recovery sequence depends on the state of the X bit.
If X is set to zero (XIRQ not masked), the MCU startsup, beginning with the stacking sequence leading to normal service of the XIRQ request. If X is set to one (XIRQ masked or inhibited), then processing continues withthe instruction that immediately follows the STOP instruction, and no XIRQ interruptservice is requested or pending.Because the oscillator is stopped in STOP mode, a restart delay may be imposed toallow oscillator stabilization upon leaving STOP.
If the internal oscillator is being used,this delay is required; however, if a stable external oscillator is being used, the DLYcontrol bit can be used to bypass this startup delay. The DLY control bit is set by resetand can be optionally cleared during initialization. If the DLY equal to zero option isused to avoid startup delay on recovery from STOP, then reset should not be used asthe means of recovering from STOP, as this causes DLY to be set again by reset, imM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-175posing the restart delay. This same delay also applies to power-on reset, regardlessof the state of the DLY control bit, but does not apply to a reset while the clocks arerunning.5MOTOROLA5-18RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATASECTION 6 PARALLEL INPUT/OUTPUTAll M68HC11 E-series MCUs have five I/O ports and up to 38 input/output lines, depending on the operating mode.
Refer to Table 6-1, which is a summary of the portsand their shared functions.Table 6-1 Input/Output PortsPortInputPinsOutputPinsBidirectionalPinsShared FunctionsPort A332TimerPort B—8—High Order AddressPort C——8Low Order Address and Data BusPort D——6SCI and SPIPort E8——A/D ConverterPort pin function is mode dependent. Do not confuse pin function with the electricalstate of the pin at reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs. I/O pins configured as high-impedance inputs haveport data that is indeterminate. The contents of the corresponding latches are dependent upon the electrical state of the pins during reset.
In port descriptions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset areshown with a value of either one or zero. Some control bits are unaffected by reset.Reset states for these bits are indicated with a "U".6.1 Port APort A, which has three input-only pins, three output-only pins, and two bidirectional I/O pins, shares functions with the timer system.PORTA — Port A DataRESET:Alt. Func:And/or:Bit 7PA7IPAIOC1$10006PA60OC2OC15PA50OC3OC14PA40OC4OC13PA3IIC4/OC5OC12PA2IIC1—1PA1IIC2—Bit 0PA0IIC3—PACTL — Pulse Accumulator ControlRESET:Bit 7DDRA70M68HC11 E SERIESTECHNICAL DATA6PAEN05PAMOD0$10264PEDGE03DDRA30PARALLEL INPUT/OUTPUT2I4/O501RTR10Bit 0RTR00MOTOROLA6-16DDRA7 — Data Direction for Port A Bit 7Overridden if an output compare function is configured to control the PA7 pin0 = Input1 = OutputThe pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be usedas general-purpose I/O or as an output compare.
Note that even when port A bit 7 isconfigured as an output, the pin still drives the input to the pulse accumulator.PAEN — Pulse Accumulator System EnableRefer to SECTION 9 TIMING SYSTEM.PAMOD — Pulse Accumulator ModeRefer to SECTION 9 TIMING SYSTEM.PEDGE — Pulse Accumulator Edge ControlRefer to SECTION 9 TIMING SYSTEM.6DDRA3 — Data Direction for Port A Bit 3Overridden if an output compare function is configured to control the PA3 pin.0 = Input1 = OutputI4/O5 — Input Capture 4/Output Compare 5Refer to SECTION 9 TIMING SYSTEM.RTR[1:0] — RTI Interrupt Rate SelectRefer to SECTION 9 TIMING SYSTEM.6.2 Port BIn single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test modes, port B pins are high order address outputs.PORTB — Port B DataS.
Chip orBoot:RESET:Expan. orTest:$1004Bit 7PB7PB76PB6PB65PB5PB54PB4PB43PB3PB32PB2PB21PB1PB1Bit 0PB0PB00ADDR150ADDR140ADDR130ADDR120ADDR110ADDR100ADDR90ADDR86.3 Port CIn single-chip and bootstrap modes, port C pins reset to high impedance inputs (DDRCbits are set to zero). In expanded and special test modes, port C pins are multiplexedaddress/data bus and the port C register address is treated as an external memory location.MOTOROLA6-2PARALLEL INPUT/OUTPUTM68HC11 E SERIESTECHNICAL DATAPORTC — Port C DataS.
Chip orBoot:RESET:Expan.or Test:$1003Bit 7PC7PC76PC6PC65PC5PC54PC4PC43PC3PC32PC2PC21PC1PC1Bit 0PC0PC0IADDR7DATA7IADDR6DATA6IADDR5DATA5IADDR4DATA4IADDR3DATA3IADDR2DATA2IADDR1DATA1IADDR0DATA0PORTCL — Port C LatchedRESET:Bit 7PCL7I6PCL6I$10055PCL5I4PCL4I3PCL3I2PCL2I1PCL1IBit 0PCL0IPORTCL is used in the handshake clearing mechanism. When an active edge occurson the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into PORTCL and clear STAF flag (following a readof PIOC with STAF set).DDRC — Data Direction Register for Port CRESET:Bit 7DDC706DDC605DDC504DDC40$10073DDC302DDC201DDC10Bit 0DDC00DDC[7:0] — Data Direction for Port C0 = Input1 = OutputIn handshake output mode, DDRC bits select the three-stated output option (DDCx =1).6.4 Port DIn all modes, port D bits [5:0] can be used either for general-purpose I/O, or with theSCI and SPI subsystems.
During reset, port D pins PD[5:0] are configured as high impedance inputs (DDRD bits cleared).PORTD — Port D DataRESET:Alt. Func.:Bit 70—__M68HC11 E SERIESTECHNICAL DATA$100860—__5PD5IPD5SS4PD4IPD4SCK3PD3IPD3MOSIPARALLEL INPUT/OUTPUT2PD2IPD2MISO1PD1IPD1TxBit 0PD0IPD0RxDMOTOROLA6-36DDRD — Data Direction Register for Port DRESET:Bit 7—06—05DDD504DDD40$10093DDD302DDD201DDD10Bit 0DDD00Bits [7:6] — Not implementedAlways read zeroDDD[5:0] — Data Direction for Port DWhen DDRD bit 5 is one and MSTR = 1 in SPCR, PD5/SS is a general-purpose outputand mode fault logic is disabled.0 = Input1 = Output6.5 Port E6Port E is used for general-purpose static inputs or pins that share functions with the A/D converter system.
When some port E pins are being used for general-purpose inputand others are being used as A/D inputs, PORTE should not be read during the sample portion of an A/D conversion.PORTE — Port E DataRESET:Alt.Func.:$100ABit 7PE7I6PE6I5PE5I4PE4I3PE3I2PE2I1PE1IBit 0PE0IAN7AN6AN5AN4AN3AN2AN1AN06.6 Handshake ProtocolSimple and full handshake input and output functions are available on ports B and Cpins in single-chip mode.
In simple strobed mode, port B is a strobed output port andport C is a latching input port. The two activities are available simultaneously.The STRB output is pulsed for two E-clock periods each time there is a write to thePORTB register. The INVB bit in the PIOC register controls the polarity of STRB pulses. Port C levels are latched into the alternate port C latch (PORTCL) register on eachassertion of the STRA input.
STRA edge select, flag, and interrupt enable bits are located in the PIOC register. Any or all of the port C lines can still be used as generalpurpose I/O while in strobed input mode.Full handshake modes use port C pins and the STRA and STRB lines. Input and output handshake modes are supported, and output handshake mode has a three-statedvariation. STRA is an edge-detecting input and STRB is a handshake output. Controland enable bits are located in the PIOC register.In full input handshake mode, the MCU asserts STRB to signal an external system thatit is ready to latch data.
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