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Also, if the slave writes data to the SPI data register (SPDR)while SS is low, a write collision error results.When CPHA equals one, the SS line can remain low between successive transfers.8.3 SPI SignalsThe following paragraphs contain descriptions of the four SPI signals: master in slaveout (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS).M68HC11 E SERIESTECHNICAL DATASERIAL PERIPHERAL INTERFACEMOTOROLA8-38Any SPI output line must have its corresponding data direction bit in DDRD registerset. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes ageneral-purpose input.
All SPI input lines are forced to act as inputs regardless of thestate of the corresponding DDR bits in DDRD register.8.3.1 Master In Slave OutMISO is one of two unidirectional serial data signals. It is an input to a master deviceand an output from a slave device. The MISO line of a slave device is placed in thehigh-impedance state if the slave device is not selected.8.3.2 Master Out Slave InThe MOSI line is the second of the two unidirectional serial data signals.
It is an outputfrom a master device and an input to a slave device. The master device places dataon the MOSI line a half-cycle before the clock edge that the slave device uses to latchthe data.88.3.3 Serial ClockSCK, an input to a slave device, is generated by the master device and synchronizesdata movement in and out of the device through the MOSI and MISO lines. Master andslave devices are capable of exchanging a byte of information during a sequence ofeight clock cycles.There are four possible timing relationships that can be chosen by using control bitsCPOL and CPHA in the serial peripheral control register (SPCR).
Both master andslave devices must operate with the same timing. The SPI clock rate select bits,SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,SPR[1:0] have no effect on the operation of the SPI.8.3.4 Slave SelectThe slave select (SS) input of a slave device must be externally asserted before amaster device can exchange data with the slave device.
SS must be low before datatransactions and must stay low for the duration of the transaction.The SS line of the master must be held high. If it goes low, a mode fault error flag(MODF) is set in the serial peripheral status register (SPSR). To disable the mode faultcircuit, write a one in bit 5 of the port D data direction register. This sets the SS pin toact as a general-purpose output rather than the dedicated input to the slave select circuit, thus inhibiting the mode fault flag. The other three lines are dedicated to the SPIwhenever the serial peripheral interface is on.The state of the master and slave CPHA bits affects the operation of SS.
CPHA settings should be identical for master and slave. When CPHA = 0, the shift clock is theOR of SS with SCK. In this clock phase mode, SS must go high between successivecharacters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line canbe tied to VSS as long as only CPHA = 1 clock mode is used.MOTOROLA8-4SERIAL PERIPHERAL INTERFACEM68HC11 E SERIESTECHNICAL DATA8.4 SPI System ErrorsTwo system errors can be detected by the SPI system.
The first type of error arises ina multiple-master system when more than one SPI device simultaneously tries to bea master. This error is called a mode fault. The second type of error, write collision,indicates that an attempt was made to write data to the SPDR while a transfer was inprogress.When the SPI system is configured as a master and the SS input line goes to activelow, a mode fault error has occurred — usually because two devices have attemptedto act as master at the same time.
In cases where more than one device is concurrently configured as a master, there is a chance of contention between two pin drivers. Forpush-pull CMOS drivers, this contention can cause permanent damage. The modefault mechanism attempts to protect the device by disabling the drivers. The MSTRcontrol bit in the SPCR and all four DDRD control bits associated with the SPI arecleared and an interrupt is generated subject to masking by the SPIE control bit andthe I bit in the CCR.Other precautions may need to be taken to prevent driver damage.
If two devices aremade masters at the same time, mode fault does not help protect either one unlessone of them selects the other as slave. The amount of damage possible depends onthe length of time both devices attempt to act as master.A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is not double buffered in the transmit direction, writes to SPDR causedata to be written directly into the SPI shift register. Because this write corrupts anytransfer in progress, a write collision error is generated.
The transfer continues undisturbed, and the write data that caused the error is not written to the shifter.A write collision is normally a slave error because a slave has no control over when amaster initiates a transfer. A master knows when a transfer is in progress, so there isno reason for a master to generate a write-collision error, although the SPI logic candetect write collisions in both master and slave devices.The SPI configuration determines the characteristics of a transfer in progress. For amaster, a transfer begins when data is written to SPDR and ends when SPIF is set.For a slave with CPHA equal to zero, a transfer starts when SS goes low and endswhen SS returns high. In this case, SPIF is set at the middle of the eighth SCK cyclewhen data is transferred from the shifter to the parallel data register, but the transferis still in progress until SS goes high.
For a slave with CPHA equal to one, transfer begins when the SCK line goes to its active level, which is the edge at the beginning ofthe first SCK cycle. The transfer ends in a slave in which CPHA equals one when SPIFis set.8.5 SPI RegistersThe three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and datastorage functions.
Refer to the following information for a description of how these registers are organized.M68HC11 E SERIESTECHNICAL DATASERIAL PERIPHERAL INTERFACEMOTOROLA8-588.5.1 Serial Peripheral ControlSPCR — Serial Peripheral Control RegisterRESET:Bit 7SPIE06SPE05DWOM04MSTR0$10283CPOL02CPHA11SPR1UBit 0SPR0USPIE — Serial Peripheral Interrupt EnableSet the SPE bit to one to request a hardware interrupt sequence each time the SPIFor MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit inthe condition code register is one.0 = SPI system interrupts disabled1 = SPI system interrupts enabled8SPE — Serial Peripheral System EnableWhen the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the SPI function.
If the SPI is in the master mode and DDRD bit 5 is set, then the port D bit 5 pinbecomes a general-purpose output instead of the SS input.0 = SPI system disabled1 = SPI system enabledDWOM — Port D Wired-OR ModeDWOM affects all port D pins.0 = Normal CMOS outputs1 = Open-drain outputsMSTR — Master Mode SelectIt is customary to have an external pull-up resistor on lines that are driven by opendrain devices.0 = Slave mode1 = Master modeCPOL — Clock PolarityWhen the clock polarity bit is cleared and data is not being transferred, the SCK pin ofthe master device has a steady state low value.
When CPOL is set, SCK idles high.Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.CPHA — Clock PhaseThe clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPHA bit selects one of two different clockingprotocols. Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.SPR[1:0] — SPI Clock Rate SelectsThese two bits select the SPI clock (SCK) rate when the device is configured as master. When the device is configured as slave, these bits have no effect. Refer to Table8-1.MOTOROLA8-6SERIAL PERIPHERAL INTERFACEM68HC11 E SERIESTECHNICAL DATATable 8-1 SPI Clock RatesSPR[1:0]DivideE-Clock ByFrequency atFrequency atFrequency atE = 1 MHz (Baud) E = 2 MHz (Baud) E = 3 MHz (Baud)002500 kHz1.0 MHz1.5 MHz014250 kHz500 kHz750 kHz101662.5 kHz125 kHz187.5 kHz113231.3 kHz62.5 kHz93.8 kHz8.5.2 Serial Peripheral StatusSPSR — Serial Peripheral Status RegisterRESET:Bit 7SPIF06WCOL05—04MODF0$10293—02—01—0Bit 0—0SPIF — SPI Interrupt Complete FlagSPIF is set upon completion of data transfer between the processor and the externaldevice.
If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. UnlessSPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.WCOL — Write CollisionClearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.0 = No write collision1 = Write collisionBit 5 — Not implementedAlways reads zeroMODF — Mode FaultTo clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR.
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