11ETD (1086184), страница 14
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The timer overflow interrupt flag and all eight timer function interrupt flagsare cleared. All nine timer interrupts are disabled because their mask bits have beencleared.The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5;however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does notcontrol the PA3 pin.5.2.4 Real-Time Interrupt (RTI)The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts aremasked. The rate control bits are cleared after reset and can be initialized by softwarebefore the real-time interrupt (RTI) system is used.5.2.5 Pulse AccumulatorThe pulse accumulator system is disabled at reset so that the pulse accumulator input(PAI) pin defaults to being a general-purpose input pin.5.2.6 Computer Operating Properly (COP)The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared, and disabled if NOCOP is set.
The COP rate is set for the shortest duration timeout.5.2.7 Serial Communications Interface (SCI)The reset condition of the SCI system is independent of the operating mode. At reset,the SCI baud rate control register (BAUD) is initialized to $04. All transmit and receiveinterrupts are masked and both the transmitter and receiver are disabled so the portpins default to being general-purpose I/O lines. The SCI frame format is initialized toM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-55an 8-bit character size.
The send break and receiver wakeup functions are disabled.The TDRE and TC status bits in the SCI status register (SCSR) are both ones, indicating that there is no transmit data in either the transmit data register or the transmitserial shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related statusbits in the SCI control register 2 (SCCR2) are cleared.5.2.8 Serial Peripheral Interface (SPI)The SPI system is disabled by reset. The port pins associated with this function defaultto being general-purpose I/O lines.5.2.9 Analog-to-Digital ConverterThe A/D converter configuration is indeterminate after reset.
The ADPU bit is clearedby reset, which disables the A/D system. The conversion complete flag is indeterminate.55.2.10 SystemThe EEPROM programming controls are disabled, so the memory system is configured for normal read operation. PSEL[3:0] are initialized with the value %0110, causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin isconfigured for level-sensitive operation (for wired-OR systems). The RBOOT, SMOD,and MDA bits in the HPRIO register reflect the status of the MODB and MODA inputsat the rising edge of reset. MODA and MODB inputs select one of the four operatingmodes.
After reset, writing SMOD and MDA in special modes causes the MCU tochange operating modes. Refer to the description of HPRIO register in SECTION 4OPERATING MODES AND ON-CHIP MEMORY for a detailed description of SMODand MDA. The DLY control bit is set to specify that an oscillator start-up delay is imposed upon recovery from STOP mode. The clock monitor system is disabled because CME is cleared.5.3 Reset and Interrupt PriorityResets and interrupts have a hardware priority that determines which reset or interruptis serviced first when simultaneous requests occur. Any maskable interrupt can be given priority over other maskable interrupts.The first six interrupt sources are not maskable.
The priority arrangement for thesesources is as follows:1.2.3.4.5.6.POR or RESET pinClock monitor resetCOP watchdog resetXIRQ interruptIllegal opcode interruptSoftware interrupt (SWI)MOTOROLA5-6RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATAThe maskable interrupt sources have the following priority arrangement:1. IRQ2.
Real-time interrupt3. Timer input capture 14. Timer input capture 25. Timer input capture 36. Timer output compare 17. Timer output compare 28. Timer output compare 39. Timer output compare 410. Timer input capture 4/output compare 511. Timer overflow12. Pulse accumulator overflow13. Pulse accumulator input edge14. SPI transfer complete15. SCI system (Refer to Figure 5-3)Any one of these interrupts can be assigned the highest maskable interrupt priority bywriting the appropriate value to the PSEL bits in the HPRIO register.
Otherwise, thepriority arrangement remains the same. An interrupt that is assigned highest priority isstill subject to global masking by the I bit in the CCR, or by any associated local bits.Interrupt vectors are not affected by priority assignment. To avoid race conditions, HPRIO can only be written while I-bit interrupts are inhibited.5.3.1 Highest Priority Interrupt and Miscellaneous RegisterHPRIO — Highest Priority I-Bit Interrupt and MiscellaneousBit 7RBOOT165SMOD100100011$103CMDA14IRVNE3PSEL32PSEL21PSEL1Bit 0PSEL0010100010000111111110000RESET:Single ChipExpandedBootstrapSpecial TestNOTES:1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode during power-up.
Refer to Table 4-2.RBOOT — Read Bootstrap ROMHas meaning only when the SMOD bit is a one (bootstrap mode or special test mode).At all other times this bit is clear and cannot be written. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.SMOD — Special Mode SelectThis bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer toSECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.MDA — Mode Select AThe mode select A bit reflects the status of the MODA input pin at the rising edge ofM68HC11 E SERIESTECHNICAL DATARESETS AND INTERRUPTSMOTOROLA5-75reset. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for moreinformation.IRVNE — Internal Read Visibility/Not EThe IRVNE control bit allows internal read accesses to be available on the externaldata bus during operation in expanded modes.
In single-chip and bootstrap modes,IRVNE determines whether the E clock is driven out an external pin. For theMC68HC811E2, this bit is IRV and only controls internal read visibility. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.PSEL[3:0] — Priority Select BitsThese bits select one interrupt source to be elevated above all other I-bit-relatedsources and can be written only while the I bit in the CCR is set (interrupts disabled).Table 5-3 Highest Priority Interrupt SelectionPSEL[3:0]5Interrupt Source Promoted0000Timer Overflow0001Pulse Accumulator Overflow0010Pulse Accumulator Input Edge0011SPI Serial Transfer Complete0100SCI Serial System0101Reserved (Default to IRQ)0110IRQ (External Pin or Parallel I/O)0111Real-Time Interrupt1000Timer Input Capture 11001Timer Input Capture 21010Timer Input Capture 31011Timer Output Compare 11100Timer Output Compare 21101Timer Output Compare 31110Timer Output Compare 41111Timer Input Capture 4/Output Compare 55.4 InterruptsThe MCU has 18 interrupt vectors that support 22 interrupt sources.
The 15 maskableinterrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) isclear. The three nonmaskable interrupt sources are illegal opcode trap, software interrupt, and XIRQ pin.
Refer to Table 5-4, which shows the interrupt sources and vectorassignments for each source.MOTOROLA5-8RESETS AND INTERRUPTSM68HC11 E SERIESTECHNICAL DATATable 5-4 Interrupt and Reset Vector AssignmentsVector AddressFFC0, C1 – FFD4, D5FFD6, D7Interrupt SourceReservedSCI Serial SystemCCRMask BitLocalMask——I• SCI Receive Data Register FullRIE• SCI Receiver OverrunRIE• SCI Transmit Data Register EmptyTIE• SCI Transmit CompleteTCIE• SCI Idle Line DetectILIEFFD8, D9SPI Serial Transfer CompleteISPIEFFDA, DBPulse Accumulator Input EdgeIPAIIFFDC, DDPulse Accumulator OverflowIPAOVIFFDE, DFTimer OverflowITOIFFE0, E1Timer Input Capture 4/Output Compare 5II4/O5IFFE2, E3Timer Output Compare 4IOC4IFFE4, E5Timer Output Compare 3IOC3IFFE6, E7Timer Output Compare 2IOC2IFFE8, E9Timer Output Compare 1IOC1IFFEA, EBTimer Input Capture 3IIC3IFFEC, EDTimer Input Capture 2IIC2IFFEE, EFTimer Input Capture 1IIC1IFFF0, F1Real-Time InterruptIRTIIFFF2, F3IRQ (External Pin)INoneFFF4, F5XIRQ PinXNoneFFF6, F7Software InterruptNoneNoneFFF8, F9Illegal Opcode TrapNoneNoneFFFA, FBCOP FailureNoneNOCOPFFFC, FDClock Monitor FailNoneCMEFFFE, FFRESETNoneNoneFor some interrupt sources, such as the SCI interrupts, the flags are automaticallycleared during the normal course of responding to the interrupt requests.
For example,the RDRF flag in the SCI system is cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF is set, followed by a read of theSCI data register. The normal response to an RDRF interrupt request would be to readthe SCI status register to check for receive errors, then to read the received data fromthe SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any special instructions.5.4.1 Interrupt Recognition and Register StackingAn interrupt can be recognized at any time after it is enabled by its local mask, if any,and by the global mask bit in the CCR. Once an interrupt source is recognized, theCPU responds at the completion of the instruction being executed.
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