CPM2A_PROGRAMMING MANUAL (W353-E1-2) (986750), страница 65
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(The hexadecimal “F” in the first digitacts as a minus sign.)The PV can be 0000 0000 to 1677 7215 in increment mode.When the output is used for synchronized pulse control, PRV(62) reads the inputfrequency and writes the 8-digit BCD value in D and D+1. The input frequencycan be 0000 0000 to 0002 0000.Interrupt Input PV (P=100 to 103)PRV(62) reads the PV of the specified interrupt input (counter mode) and writesthe 4-digit hexadecimal value (0000 to FFFF) in D.Read Status (C=001)If C is 001, PRV(62) reads the operating status of the specified high-speedcounter or pulse output and writes the data to D.High-speed Counter or Pulse Output 0 Status (P=000)The following table shows the function of the bits in D when P=000.
Bits not listedin the table are not used and will always be 0.UsageHigh-speedcounterBit0001Pulse output0506070809FunctionHigh-speed counter comparison status.(0: Stopped; 1: Comparing)High-speed counter underflow/overflow.(0: Normal; 1: Underflow/Overflow occurred.)Total number of pulses specified for pulse output 0.(0: Not specified; 1: Specified.)Pulse output 0 completed. (0: Not completed; 1: Completed)Pulse output 0 status (0: Stopped; 1: Outputting)Pulse output 0 PV underflow/overflow.(0: Normal; 1: Underflow/Overflow occurred.)Pulse output 0 acceleration0: Constant; 1: Accelerating or deceleratingPulse Output 1 Status (P=010)The following table shows the function of the bits in D when P=010.
Bits not listedin the table are not used and will always be 0.Bit05Function06Total number of pulses specified for pulse output 1.(0: Not specified; 1: Specified.)Pulse output 1 completed. (0: Not completed; 1: Completed)07Pulse output 1 status (0: Stopped; 1: Outputting)08Pulse output 1 PV underflow/overflow.(0: Normal; 1: Underflow/Overflow occurred.)Pulse output 1 acceleration (0: Constant; 1: Accelerating or decelerating)09Read Range ComparisonResults (C=002)If C is 002, PRV(62) reads the results of the comparison of the PV to the 8 rangesdefined by CTBL(63) and writes this data to D. Bits 00 through 07 of D containthe Comparison Result Flags for ranges 1 to 8.
(0: Not in range; 1: In range)Read Pulse Output PV(C=003)If C is 003, PRV(62) reads the pulse output PV and writes the 8-digit BCD valuein D and D+1. (The leftmost 4 digits are written to D+1.)The PV can be –16,777,215 to 16,777,215. Bit 15 of D+1 acts as a sign bit; thenumber is negative if bit 15 is ON, positive if it is OFF.372Section 7-15Timer and Counter InstructionsFlagsER:The port specifier and control data are incompatible.(For example: P=010 and C=000)The address specified for D or D+1 exceeds the data area boundary.There is an error in the operand settings.Indirectly addressed DM word is non-existent.
(Content of *DM word isnot BCD, or the DM area boundary has been exceeded.)PRV(62) is executed in an interrupt subroutine while a pulse I/O or highspeed counter instruction (INI(61), PRV(62), CTBL(63), SPED(64),PULS(65), ACC(––), PWM(––), or SYNC(––)) is being executed in themain program.373Section 7-16Shift Instructions7-16 Shift Instructions7-16-1 SHIFT REGISTER – SFT(10)Ladder SymbolOperand Data AreasSt: Starting wordISFT(10)IR, SR, AR, HR, LRPStREE: End wordIR, SR, AR, HR, LRE must be greater than or equal to St, and St and E must be in the same dataarea.LimitationsIf a bit address in one of the words used in a shift register is also used in aninstruction that controls individual bit status (e.g., OUT, KEEP(11)), an error(“COIL/OUT DUPL”) will be generated when program syntax is checked on theProgramming Console or another Programming Device.
The program, however, will be executed as written. See Example 2: Controlling Bits in Shift Registersfor a programming example that does this.DescriptionSFT(10) is controlled by three execution conditions, I, P, and R. If SFT(10) isexecuted and 1) execution condition P is ON and was OFF the last execution,and 2) R is OFF, then execution condition I is shifted into the rightmost bit of ashift register defined between St and E, i.e., if I is ON, a 1 is shifted into the register; if I is OFF, a 0 is shifted in.
When I is shifted into the register, all bits previouslyin the register are shifted to the left and the leftmost bit of the register is lost.ESt+1, St+2, ...Lost dataStExecution condition IThe execution condition on P functions like a differentiated instruction, i.e., I willbe shifted into the register only when P is ON and was OFF the last time SFT(10)was executed. If execution condition P has not changed or has gone from ON toOFF, the shift register will remain unaffected.St designates the rightmost word of the shift register; E designates the leftmost.The shift register includes both of these words and all words between them. Thesame word may be designated for St and E to create a 16-bit (i.e., 1-word) shiftregister.When execution condition R goes ON, all bits in the shift register will be turnedOFF (i.e., set to 0) and the shift register will not operate until R goes OFF again.Flags374ER:St and E are not in the same area or St is greater than E.Section 7-16Shift InstructionsExampleThe following example uses the 1-second clock pulse bit (25502) so that theexecution condition produced by 00000 is shifted into HR 00 every second.
Output 20000 is turned ON whenever a “1” is shifted into HR 0007.00000AddressISFT(10)25502PHR 0000001RHR 00000720000Instruction00000000010000200003LDLDLDSFT(10)0000400005LDOUTOperandsHRHRHR00000255020000100000007200007-16-2 WORD SHIFT – WSFT(16)Ladder SymbolsOperand Data AreasSt: Starting wordWSFT(16)@WSFT(16)StStEEIR, SR, AR, DM, HR, LRE: End wordIR, SR, AR, DM, HR, LRLimitationsSt and E must be in the same data area, and E must be greater than or equal toSt.DM 6144 to DM 6655 cannot be used for St or E.DescriptionWhen the execution condition is OFF, WSFT(16) is not executed. When theexecution condition is ON, WSFT(16) shifts data between St and E in word units.Zeros are written into St and the content of E is lost.EF0St + 1C 2345St21029Lost0000E3FlagsER:4St + 152102St90000The St and E words are in different areas, or St is greater than E.Indirectly addressed DM word is non-existent.
(Content of *DM word isnot BCD, or the DM area boundary has been exceeded.)7-16-3 ARITHMETIC SHIFT LEFT – ASL(25)Ladder SymbolsLimitationsOperand Data AreasASL(25)@ASL(25)WdWdWd: Shift wordIR, SR, AR, DM, HR, LRDM 6144 to DM 6655 cannot be used for Wd.375Section 7-16Shift InstructionsDescriptionWhen the execution condition is OFF, ASL(25) is not executed.
When the execution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd onebit to the left, and shifts the status of bit 15 into CY.CYBitBit15001 0 0 1 1 1 0 0 0 1 0 1 0 0 1 10PrecautionsA 0 will be shifted into bit 00 every cycle if the undifferentiated form of ASL(25) isused. Use the differentiated form (@ASL(25)) or combine ASL(25) withDIFU(13) or DIFD(14) to shift just one time.FlagsER:Indirectly addressed DM word is non-existent. (Content of *DM word isnot BCD, or the DM area boundary has been exceeded.)Receives the status of bit 15.ON when the content of Wd is zero; otherwise OFF.CY:EQ:7-16-4 ARITHMETIC SHIFT RIGHT – ASR(26)Ladder SymbolsOperand Data AreasASR(26)@ASR(26)WdWdWd: Shift wordIR, SR, AR, DM, HR, LRLimitationsDM 6144 to DM 6655 cannot be used for Wd.DescriptionWhen the execution condition is OFF, ASR(25) is not executed.
When theexecution condition is ON, ASR(25) shifts a 0 into bit 15 of Wd, shifts the bits ofWd one bit to the right, and shifts the status of bit 00 into CY.BitBit15001 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0CY0PrecautionsA 0 will be shifted into bit 15 every cycle if the undifferentiated form of ASR(26) isused. Use the differentiated form (@ASR(26)) or combine ASR(26) withDIFU(13) or DIFD(14) to shift just one time.FlagsER:Indirectly addressed DM word is non-existent.
(Content of *DM word isnot BCD, or the DM area boundary has been exceeded.)Receives the data of bit 00.ON when the content of Wd is zero; otherwise OFF.CY:EQ:7-16-5 ROTATE LEFT – ROL(27)Ladder SymbolsLimitations376Operand Data AreasROL(27)@ROL(27)WdWdDM 6144 to DM 6655 cannot be used for Wd.Wd: Rotate wordIR, SR, AR, DM, HR, LRSection 7-16Shift InstructionsDescriptionPrecautionsWhen the execution condition is OFF, ROL(27) is not executed. When theexecution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shiftingCY into bit 00 of Wd and shifting bit 15 of Wd into CY.CYBit15Bit0001 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1Use STC(41) to set the status of CY or CLC(41) to clear the status of CY beforedoing a rotate operation to ensure that CY contains the proper status beforeexecuting ROL(27).CY will be shifted into bit 00 every cycle if the undifferentiated form of ROL(27) isused.
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