CPM2A_PROGRAMMING MANUAL (W353-E1-2) (986750), страница 16
Текст из файла (страница 16)
(4 digits BCD): 0000 to 00491. When C2 is entered as a word address:C2: Decrementing counter set value (4 digits BCD): 0000 to 9999C2 + 1: Decrementing time interval (4 digits BCD; unit: 0.1 ms): 0005 to 0320(0.5 ms to 32 ms)The meanings of the settings are the same as for the one-shot mode, but inthe scheduled interrupt mode the timer PV will be reset to the set value anddecrementing will begin again after the subroutine has been called. In thescheduled interrupt mode, interrupts will continue to be repeated at fixed intervals until the operation is stopped.SectionCPM1/CPM1A Interrupt Functions2-32. When C2 is entered as a constant:The settings are the same as for the one-shot mode, but interrupts will continue to be repeated at fixed intervals until the operation is stopped.Reading the Timer’s Elapsed TimeUse the STIM(69) instruction to read the timer’s elapsed time.(@)STIM(69)C1C2C3C1: Read elapsed time (006)C2: Leading word of parameter 1C3: Parameter 2C2: Number of times the decrementing counter has ben decremented (4 digitsBCD)C2 + 1: Decrementing counter time interval (4 digits BCD; unit: 0.1 ms)C3: Elapsed time from previous decrement (4 digits BCD; unit: 0.1 ms)The time from when the interval timer is started until the execution of this instruction is calculated as follows:{(Content of C2) × (Content of C2+1) + (Content of C3)} × 0.1 msIf the specified interval timer is stopped, then “0000” will be stored.Stopping the TimerUse the STIM(69) instruction to stop the interval timer.
The interval timer will bestopped.(@)STIM(69)C1C1: Stop interval timer (010)000000Application Example(One-shot Mode)In this example, an interrupt is generated 2.4 ms (0.6 ms × 4) after input 00005goes ON; the interrupt executes interrupt subroutine number 23.25315 First Cycle FlagON for 1 cycleMOV(21)#0004DM 0010Sets the decrementing counter‘s set value to 4.(BCD: 0000 to 9999)MOV(21)#0006DM 0011Sets the decrementing time interval to 0.6 ms.(BCD: 0005 to 0320)00005@STIM(69)000DM 0010#0023SBN(92)Starts the interval timer in one-shot mode.Specifies the first word containing the set value.Specifies the subroutine number (23).023Interrupt programRET(93)77SectionCPM1/CPM1A Interrupt FunctionsApplication Example(Scheduled Interrupt Mode)2-3In this example, an interrupt is generated every 4.0 ms (1.0 ms × 4) after input00005 goes ON; the interrupts execute interrupt subroutine number 23.25315 First Cycle FlagON for 1 cycleMOV(21)#0004DM 0010Sets the decrementing counter‘s set value to 4.(BCD: 0000 to 9999)MOV(21)#0010DM 0011Sets the decrementing time interval to 1.0 ms.(BCD: 0005 to 0320)00005@STIM(69)003DM 0010#0023SBN(92)Starts the interval timer in scheduled interrupt mode.Specifies the first word containing the set value.Specifies the subroutine number (23).023Interrupt programRET(93)2-3-5 High-speed Counter InterruptsCPM1/CPM1A PCs have a high-speed counter function that can be used in incrementing mode or up/down mode.
The high-speed counter can be combinedwith input interrupts to perform target value control or zone comparison controlthat isn’t affected by the PC’s cycle time.High-speed counter signals can be input to CPU bits 00000 through 00002.NC24VDC78000020000100000CPM1 PCsSectionCPM1/CPM1A Interrupt Functions2-3CPM1A PCsModeInput functionsInput methodUp/Down00000: Phase-A input00001: Phase-B input00002: Phase-Z inputIncrementing00000: Count input00001: See note.00002: Reset inputCountCountfrequencyrangePhase-difference, 2.5 kHz max. –327674× inputsto32767Individual inputs5.0 kHz max.
0to65535Control methodsTarget value control:Up to 16 target values andinterrupt subroutine numbers canbe registered.Zone comparison control:Up to 8 sets of upper limit values,lower limit values, and interruptsubroutine numbers can beregistered.Note In incrementing mode, input 00001 can be used as a regular input. When thereset method is used for the software reset, input 00002 can be used as a regularinput. Also, even when used for the phase-Z signal and software reset, the inputstatus is reflected inn 00002 of the I/O memory.High-speed Counter Settings The following settings must be made in DM 6642 when using theCPM1/CPM1A’s high-speed counter function.DM 6642BitsSettingsFunction00 to 03Sets the counter mode:Incrementing Up/Down40Not used0 or 404 to 070: Up/down4: IncrementingSets the reset method:0 or 10 or 10 or 108 to 150: Phase-Z + software reset1: Software resetSets the counter:01010000: Counter not being used.01: Counter being used.Count RangeThe CPM1/CPM1A’s high-speed counter uses linear operation and the count(present value) is stored in SR 248 and SR 249.
(The upper four digits are storedin SR 249 and the lower four digits are stored in SR 248.)ModeCount rangeUp/DownF003 2767 to 0003 2767 (–32,767 to 32,767)The leftmost digit in SR 248 indicates the sign. F is negative, 0 ispositive.Incrementing0000 0000 to 0006 5535 (0 to 65,535)79SectionCPM1/CPM1A Interrupt Functions2-3An overflow will occur if the count exceeds the upper limit in the count range andan underflow will occur if the count goes below the lower limit in the count range.ErrorOverflowUnderflowProcessingIncrementingUp/DownOccurs when the count isincremented from 65,535.---Presentvalue0FFF FFFFOccurs when the count isincremented from 32,767.Occurs when the count isFFFF FFFFdecremented from –32,767.Two types of signals can be input from a pulse encoder.
The count mode used forthe high-speed counter will depend on the signal type. The count mode and reset mode are set in DM 6642; these settings become effective when the power isturned on or PC operation is started.Up/Down Mode:Phase-A difference 4× two-phase signal (phase-A and phase-B) and aphase-Z signal are used for inputs. The count is incremented or decremented according to differences in the 2-phase signals.Incrementing Mode:One single-phase pulse signal and a count reset signal are used for inputs.The count is incremented according to the single-phase signal.Incrementing ModeUp/Down ModeONPulseinputPhase AOFFONOFFONPhase BOFFCount1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 –1 –2IncrementedDecrementedCount1234Incremented onlyNote One of the reset methods described below should always be used to reset thecounter when restarting it.
The counter will be automatically reset when programexecution is started or stopped.The following signal transitions are handled as forward (incrementing) pulses:Phase-A leading edge to phase-B leading edge to phase-A trailing edge tophase-B trailing edge. The following signal transitions are handled as reverse(decrementing) pulses: Phase-B leading edge to phase-A leading edge tophase-B trailing edge to phase-A trailing edge.The Up/Down Mode always uses a 4× phase-difference input. The number ofcounts for each encoder revolution would be 4 times the resolution of the counter.
Select the encoder based on the countable ranges.Reset MethodsEither of the two methods described below may be selected for resetting the PVof the count (i.e., setting it to 0).Phase-Z signal + software reset:The PV is reset when the phase-Z signal (reset input) is turned ON while theHigh-speed Counter Reset Bit (SR 25200) is ON.Software reset:The PV is reset when the High-speed Counter Reset Bit (SR 25200) isturned ON.80SectionCPM1/CPM1A Interrupt Functions2-3Phase-Z Signal + Software ResetI/O refreshCommon processing,communications servicing, etc.1 cycleProgramexecutionCPU processingProgramexecutionProgramexecutionProgramexecutionProgramexecutionProgramexecution25200(1)(2)(3)(4)ResetReset(5)Phase-ZNot resetNot resetNo.(1)(2)(3)(4)(5)Not resetOperation timingResetPhase-Z signal turns ON whenNot reset.SR 25200 turns OFF.Phase-Z signal turns ON within oneNot reset.cycle after SR 25200 turns ON.Phase-Z signal turns ON after at least Reset with phase-Z leading edge.one cycle elapses after SR 25200turns ON.Phase-Z signal turns ON within onecycle after SR 25200 turns OFF.SR 25200 turns ON when phase-Zsignal is ON.Reset with phase-Z leading edge.Not reset.Note The High-speed Counter Reset Bit (SR 25200) is refreshed once every cycle, soin order for it to be read reliably it must be ON for at least one cycle.The “Z” in “phase-Z” is an abbreviation for “Zero.” It is a signal that shows that theencoder has completed one cycle.High-speed Counter Interrupt CountFor high-speed counter 0 interrupts, a comparison table is used instead of a“count up.” The count check can be carried out by either of the two methods described below.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
