Roland A. - PVD for microelectronics (779636), страница 54
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For example,Fig. 9.6 shows how the electrical resistivity of both PVD Ti and PVD TiNfilms sputtered onto SiO 2 increases greatly for thickness below about 200A. Regarding thin film effects, it is worth noting that even though ULSI interconnect lines are hundreds of times thicker than their barriers and liners,thin film thinking is still appropriate. For example, nearly 50% of the A1atoms in a 0.75-/xm • 0.25-/xm interconnect line are located within 500/~of a surface or interface.9.3 AI Alloys9.3.1 METALLURGICALCONSIDERATIONSFOR PVDAluminum alloys (with a few weight percent of Si and/or Cu to preventjunction spiking and enhance electromigration resistance, respectively)used in combination with Ti and TiN cladding layers are likely to remainTINTi2 0 0'.;.;~Io'ioo1110:L~--12080.....i ..........
i. . . . . . . . i . . . . . . . " . . . . . . . .~'i ........9. . . . . . ! .......... 1.....400200400:600...2 . . . . . . . .800M1000Thickness ( A )FIG. 9.6iDependenceof resistivity!!~. . . . . . . . . i . . . . . . . . ~. . . . . . . .
~..........90......~..........i ........i .........i80.......~ ..........~ ........- .........~...................70~......... i . . . . . . . . . ~ . . . . . . . . - ........... " . . . . . . . . .5o.....i ........:~40 ......................ii30,1 ,i0200400.,for collimatedPVD..........1ii600Thi~n~on film thicknessi....ii .8001,000(A)Ti and PVDTiN.PVD MATERIALS AND PROCESSES293the dominant horizontal interconnect for 0.25-/xm (and possibly 0.18-/xm)devices.
In fact, the primary application of PVD cluster tools in productiontoday is to deposit planar films of "slab AI" interconnect as opposed to themore aspect-ratio-challenging applications of contacts and barriers. Theadvantages of A1 in microelectronics are numerous [9.9], with the following points being of special relevance to its use as a PVD interconnect.1.
The room temperature electrical resistivity of pure A1 (p = 2 . 7 / x ~ cm), although not as low as Cu, Ag, or Au, is one of the lowest among allthe metals. This resistivity is only slightly increased to ~ 3/xD,-cm whenthe A1 is alloyed with a few weight percent of Cu to improve electromigration resistance (Ap ~ 0.3 /xl~-cm for 1 wt % Cu) and/or with a fewweight percent Si to limit void formation at the m e t a l - S i interface (Ap0.7 /xl)-cm for 1 wt % Si). In any case, PVD A1 resistivity is many timeslower than that of the other films used in the M L M stack (e.g., p ~ 7 0 / ~ l ) cm for PVD Ti and TiN, p ~ 1 0 / x l ) - c m for CVD W).2.
A1 sputter targets can readily be obtained with ultrahigh purity(-> 5N5) in either elemental or alloy composition.PVD alloy film and target compositions are often given in weight percent(e.g., an AI-Si(I%)-Cu(0.5%) film or a Ti(10%)-W target) which, depending on the relative masses and concentration of the elemental constituents,can differ significantly from atomic percent (see Chapter 11). For example,1 wt % of Si or Cu in AI is equivalent to ~- 1.0 and 0.4 at %, respectively,while 10 wt % of Ti in W is equivalent to ~ 30 at %.
Therefore, in comparing results it is important that the same type of percents are being reported. This is particularly relevant for surface analytical results, which areoften given in atomic concentrations.3. The DC magnetron sputter rate of AI is high enough ( > 1 /zm/min)that blanket l-/xm AI films can be deposited with production-worthythroughput of > 40 wafers per hour.4. Although A1 is highly reactive with SiO 2 and reduces it to Si (heat offormation of A1203 is 399 Kcal/mol vs 205 Kcal/mol for SiO2), the reaction is self-limiting and stops when a sufficiently thick A1203 layer hasformed.
This ensures that when A1 is sputtered onto field oxide regions thereaction does not compromise the integrity of either the A1 wiring or theinterlayer dielectric. On the other hand, the limited reactivity of AI filmstoward SiO 2 is very important since this ensures good adherence of thePVD A1 film to the field oxide surface and to the sidewalls of a via cut294R.
POWELL AND S. M. ROSSNAGELthrough the oxide, obviating the need for a separate glue layer such as theTiN that is used between oxide and CVD W.5. A1 has a relatively low melting point ( T p = 660~with high selfdiffusion rates at moderate process temperatures ( ~ 400-550~This hasallowed a variety of elevated-temperature PVD processes such as reflowedA1 and the cold-hot A1, two-step process (TSP) to be used to improve thestep coverage and filling of A1 in high aspect ratio features (see Chapter 7).6. A1 films and A1 alloy films with moderate weight percents of Cu canbe readily patterned into interconnect lines using plasma-assisted, dryetching methods. This ability to use subtractive metal patterning (i.e., etching of a photoresist-patterned AI overlayer on oxide) means that one doesnot have to resort to a single- or dual-damascene approach in forming themultilevel metal interconnect stack, such as is the case with Cu (see Section 9.8).
Damascene processing not only removes the need for plasmaetching of the metal lines but also the need to fill the gaps between thelines with insulator. Since plasma etching of metals and dielectric gap fillare two of the most difficult processes in ULSI device fabrication, this is aconsiderable simplification. Damascene processing can require filling ofhigher aspect ratio structures such as simultaneous filling of a via andtrench; however, the potential cost savings has led to its being applied toAI as well as Cu even though a subtractive method of patterning the AIcould be used.
On the other hand, the chemical-mechanical polishing(CMP) step used to planarize lhe metal layer involves creation of an anodized metal surface. When damascene processing is applied to AI, theCMP step then requires polishing back a layer of alumina (A!203) whosehardness is greater than either CuO or SiO 2.The two major concerns about PVD AI interconnect lines are (1) theirrelatively poor electromigration (EM) resistance and (2) the effects ofstress that can result in the formation of voids within the lines (stress voiding) or the formation of protruding bumps on their surface (hillock formation). Electromigration refers to the migration of matter due to momentumexchange between the conduction electrons and AI atoms of the interconnect line.
Even though the total current flow in a thin film interconnect issmall, its microscopic cross-sectional area leads to an enormous currentdensity (10 6-7 A/cm 2 for advanced devices), which can lower device reliability and even result in catastrophic open-circuit line failure. Historically,PVD has addressed concerns about EM by depositing AI alloys with a fewweight percent of Cu and by choosing deposition conditions favoring astrongly (111) oriented film.
Also, since thinning down of the metal alongthe vertical sidewalls of via holes can lead to local heating and EM failure,PVD MATERIALSAND PROCESSES295PVD processes with improved step coverage are preferred. Concernsabout PVD film stress have been addressed by reducing process temperature and using cladding layers such as Ti and/or TiN on the A1 to "harden"it against stress voiding and hillock formation as well as to provide a lowresistance shunt should the A1 line start to void. A useful summary of filmissues associated with either thermal stress or electromigration is providedin ref. 1.15 (Chapter 8 on "Electro- and Stress-Migration in MLM Interconnect Structures," M.
L. Dreyer and P. S. Ho).9.3.2 DEPOSITION RATEAdvanced DC magnetrons are capable of depositing the 1-~m-thick A1 alloys used in a slab A1 interconnect with a uniformity of 3o" < 5% over 200mm wafers. A high rate of sputtering ( > 1 /~m/min) is also needed for production-worthy cluster tool throughput of ~ 40-60 wafers/hour.
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