Roland A. - PVD for microelectronics (779636), страница 52
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Experiments have both examined the crystallinity ofI-PVD A1 and AICu and compared results to ionized-beam depositiontechniques. In general, several results all point to a similar conclusion.The (111) texture of the AI films (on silicon dioxide) is strongly enhancedif either the relative ionization of the depositing species (at constant energy) or the kinetic energy (at constant relative ionization) is increased(Fig. 8.41) [8.26].
Another measure of this is to examine the dispersion orHG. 8.38Kelvin resistance distribution comparing I-PVD (IMP) to collimated Ti deposition [8.24].IONIZED MAGNETRON SPUTTER DEPOSITION: I-PVD3.59''~ .... ~"~I1'"'""I:,_]_~--_',.I..~.......Std. " " '00.A/I - - I I . - IMP TiN 200 Aii " ' & " " IMP TiFFiN 50 A/IO0 A !I ""4k'" IMP Til/]i'liN 100 ,/k/200 A l!1...........................f ' " - : - .
.......~ 22.5v............ i ....................iOr;"i......................... .,",~9t--9iiCk3-i281-;i,i........~................~..........................~(1)n-"9lk,"0.~9.........................."~i...........................~'.:.--.',r,.~~..,..,~..,.., , ......, , . I.'~. ...............~ 'i...........................>i1.5 ...... .0.35..ii ......0.4!i0.45.
. . . . . ..,..... --~L - . . ,........i0.5....0.550.6Via D i a m e t e r (lam)FIG. 8.39Via resistance as a function of via diameter for standard TiN and I-PVD Ti/TiN layers [8.18].degree of orientation of the (111) grains. As a function of increased AI ionenergy, this also shows a strong effect, resulting in very highly orientedfilms at higher ion energies (Fig.
8.42) [8.26]. Similar results have beenconfirmed recently [8.10].2000,E?E01000 !.~---i;5000F----tEE.=.<6o.=.>,~9ti200!I100.5o~IwJi20,0120..t......I40,160,I,80I .....1 O0a..:120Depositing Ion Energy (eV)The resistivity of 1000-,/k TiN as a function of sample bias voltage for I-PVD reactive deposition to TiN [8.25].FIG.
8.40282R. POWELL AND S. M. ROSSNAGEL--2.o . . . . . . . . . . .A~/~i0:.1.5ii1 - - - i - --w-- - 18...._~0_;_ _ . 1..34_ j L..(111)...38.!....,....~ / . . _(002)4220 (deg)IL_,-JAj+/JAt = 34 eV36%(/)t--....._...._.._]~2r0. l . . , l _ l .46-..g,27 eVThermal,.:4v3~_v.0.5,O75 eVr",AI/SiO 2Ts = 65~EAI+ = 68%E120 eV1.0.....6i._~Em.- - -(/)E' =?,.r-.rTs = 65~JAl+/JAi = 68%Eo.-v... . . . (111)-3450l....I38. . . 130%21%_iThermal-) ~(002). .I 14220 (deg)(a)1 .I46- .- I - - .
-1 .50(b)FIG. 8.41 Intensity of (111) peaks for AI films deposited on SiO 2 samples as a function of (a) increased ion energy at constant relative ionization and (b) increased relative ionization at constant ionenergy [ 8.26].15AI/SiO 2Ts = 6 5 ~JAI+/JAI =s"O;1C030%"lU..'-"68%54oOO'qO020406080100120140160EAI+ (eV)FIG. 8.42 Full width at half m a x i m u m intensity of w-rocking curves obtained from 3000-/k AI filmsgrown at 65~ using a partially ionized AI beam 18.261.IONIZED MAGNETRON SPUTTER DEPOSITION: I-PVD283References8.1. J.J. Cuomo, R.
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Vac. Sci. & Tech.A14" 346 (1996).Chapter 9 PVD Materials and Processes9.1 IntroductionThere are many excellent monographs, conference proceedings, and articles that treat microelectronic thin film metrology, properties, and processing (see Section 1.3). This chapter presents a brief overview of the keymicroelectronic materials and process sequences that are utilized in PVDfor multilevel metallization (MLM), including contact, via, and interconnect applications. Since this book is a tutorial about PVD and not thinfilms per se, this chapter will emphasize PVD-specific aspects of thin filmprocessing.
By way of introduction, Fig. 9.1 summarizes material properties of the key metallic elements encountered in PVD for microelectronics.Figure 9.2 illustrates schematically how PVD films are utilized forMLM applications in a 0.5-/xm VLSI device, and Fig. 9.3 illustrates howPVD metals might be incorporated in a 0.18-/xm ULSI device (see alsoFig.
1.3, Chapter 1). For VLSI devices, as discussed in Chapter 1, the metallurgy of PVD is dominated by relatively thick ( ~ 1 /xm) AI alloy interconnect lines - - clad with Ti and/or TiN for improved performance - - andrelatively thin ( ~ 500 A) Ti/TiN barriers, liners, and adhesion layers todeal with CVD W plugs at contact and via levels. As a result, much of thischapter deals with PVD process conditions and issues for Ti, TiN, and AIalloys. On the other hand, the desire to replace or augment AI alloys witha lower-resistance interconnect for ULSI devices has focused considerableattention on Cu and Cu-compatible barriers such as Ta and TaN. In the future, as shown in Fig.
9.3, it is likely that these films will join the list ofkey PVD materials, so this chapter also includes a discussion of PVD Cuissues.Both AI and Cu are also of interest with regard to contact and via plugs.Namely, although CVD W has been the plug fill material of choice forVLSI devices, MLM technology roadmaps indicate that W via plugs, andpossibly W contact plugs, will be replaced for ULSI devices by the moreconducting AI and/or Cu.
Another reason for moving away from W is thatit is a diffusion barrier for the critical diffusing AI and Cu species in electromigration and prevents their being replenished. As a result, void damage can occur at the via once the limited source of migrating species isdepleted. Therefore, interconnect roadmaps show W plugs being replacedby AI and/or Cu for deep submicron devices (-< 0.18/zm).
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