DE0_CV_User_Manual (1162586), страница 6

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Press KEY0 to runthe test continuously. The program will display the test progress and result, as shown in Figure 5-3.Figure 5-3 Display of progress and result for the SDRAM test in Nios IIDE0-CV User Manual47www.terasic.comJanuary 16, 20155. 3 SDRAM Test in VerilogDE0_CV system CD offers another SDRAM test with its test code written in Verilog HDL. Thememory size of the SDRAM bank tested is still 64MB. Function Block DiagramFigure 5-4 shows the function block diagram of this demonstration. The SDRAM controller uses 50MHz as a reference clock and generates 100 MHz as the memory clock.Figure 5-4 Block diagram of the SDRAM test in VerilogRW_Test module writes the entire memory with a test sequence first before comparing the data readback with the regenerated test sequence, which is same as the data written to the memory.

KEY0triggers test control signals for the SDRAM, and the LEDs will indicate the test result according toTable 5-1.Design Tools Quartus II v14.0Demonstration Source Code Project directory: DE0_CV_SDRAM_RTL_Test Bitstream used: DE0_CV_SDRAM_RTL_Test.sofDE0-CV User Manual48www.terasic.comJanuary 16, 2015Demonstration Batch FileDemo batch file folder: \DE0_CV_SDRAM_RTL_Test\demo_batchThe directory includes the following files: Batch file: DE0_CV_SDRAM_RTL_Test.bat FPGA configuration file: DE0_CV_SDRAM_RTL_Test.sofDemonstration Setup Quartus II v14.0 must be pre-installed to the host PC. Connect the DE0_CV board (J13) to the host PC with a USB cable and install the USB-Blaster IIdriver if necessary Power on the DE0_CV board. Execute the demo batch file “ DE0_CV_SDRAM_RTL_Test.bat” from the directoy\DE0_CV_SDRAM_RTL_Test \demo_batch. Press KEY0 on the DE0_CV board to start the verification process.

When KEY0 is pressed, theLEDR [2:0] should turn on. When KEY0 is then released, LEDR1 and LEDR2 should startblinking. After approximately 8 seconds, LEDR1 should stop blinking and stay ON to indicate the test isPASS. Table 5-1 lists the status of LED indicators. If LEDR2 is not blinking, it means 50MHz clock source is not working. If LEDR1 failed to remain ON after approximately 8 seconds, the SDRAM test is NG. Press KEY0 again to repeat the SDRAM test.Table 5-1 Status of LED IndicatorsNameLEDR1DescriptionON if the test is PASS after releasing KEY0LEDR2Blinks5.

4 PS/2 Mouse DemonstrationA simply PS/2 controller coded in Verilog HDL is provided to demonstrate bi-directionalcommunication with a PS/2 mouse. A comprehensive PS/2 controller can be developed based on itand more sophisticated functions can be implemented such as setting the sampling rate or resolution,which needs to transfer two data bytes at once.More information about the PS/2 protocol can be found on various websites.DE0-CV User Manual49www.terasic.comJanuary 16, 2015 IntroductionPS/2 protocol uses two wires for bi-directional communication.

One is the clock line and the otherone is the data line. The PS/2 controller always has total control over the transmission line, but it isthe PS/2 device which generates the clock signal during data transmission. Data Transmission from Device to the ControllerAfter the PS/2 mouse receives an enabling signal at stream mode, it will start sending outdisplacement data, which consists of 33 bits. The frame data is cut into three sections and each ofthem contains a start bit (always zero), eight data bits (with LSB first), one parity check bit (oddcheck), and one stop bit (always one).The PS/2 controller samples the data line at the falling edge of the PS/2 clock signal.

This isimplemented by a shift register, which consists of 33 bits.easily be implemented using a shift register of 33 bits, but be cautious with the clock domaincrossing problem. Data Transmission from the Controller to DeviceWhen the PS/2 controller wants to transmit data to device, it first pulls the clock line low for morethan one clock cycle to inhibit the current transmission process or to indicate the start of a newtransmission process, which is usually called as inhibit state. It then pulls low the data line beforereleasing the clock line. This is called the request state.

The rising edge on the clock line formed bythe release action can also be used to indicate the sample time point as for a 'start bit. The devicewill detect this succession and generates a clock sequence in less than 10ms time. The transmit dataconsists of 12bits, one start bit (as explained before), eight data bits, one parity check bit (oddcheck), one stop bit (always one), and one acknowledge bit (always zero).

After sending out theparity check bit, the controller should release the data line, and the device will detect any statechange on the data line in the next clock cycle. If there’s no change on the data line for one clockcycle, the device will pull low the data line again as an acknowledgement which means that the datais correctly received.After the power on cycle of the PS/2 mouse, it enters into stream mode automatically and disabledata transmit unless an enabling instruction is received. Figure 5-5 shows the waveform whilecommunication happening on two lines.DE0-CV User Manual50www.terasic.comJanuary 16, 2015Figure 5-5 Waveform of clock and data signals during data transmissionDemonstration Source Code Project directory: DE0_CV_PS2_DEMO Bitstream used: DE0_CV_PS2_DEMO.sofDemonstration Batch FileDemo batch file directoy: \DE0_CV_PS2_DEMO \demo_batchThe folder includes the following files: Batch file: DE0_CV_PS2_DEMO.bat FPGA configuration file : DE0_CV_PS2_DEMO.sofDE0-CV User Manual51www.terasic.comJanuary 16, 2015Demonstration Setup, File Locations, and Instructions Load the bitstream into the FPGA by executing \DE0_CV_PS2_DEMO \demo_batch\DE0_CV_PS2_DEMO.bat Plug in the PS/2 mouse Press KEY0 to enable data transfer Press KEY1 to clear the display data cache The 7-segment display should change when the PS/2 mouse moves.

The LEDR[2:0] will blinkaccording to Table 5-2 when the left-button, right-button, and/or middle-button is pressed.Table 5-2 Description of 7-segment Display and LED IndicatorsIndicator NameLEDR0LEDR1LEDR2HEX0HEX1HEX2HEX3DescriptionLeft button press indicatorRight button press indicatorMiddle button press indicatorLow byte of X displacementHigh byte of X displacementLow byte of Y displacementHigh byte of Y displacement5. 5 Micro SD Card file system readMany applications use a large external storage device, such as a SD Card or CF card to store data.The DE0-CV board provides the hardware and software needed for Micro SD Card access. In thisdemonstration we will show how to browse files stored in the root directory of an SD Card and howto read the file contents of a specific file.

The Micro SD Card is required to be formatted as FATFile System in advance. Long file name is supported in this demonstration. Figure 5-6 shows thehardware system block diagram of this demonstration. The system requires a 50MHz clockprovided by the board.

The PLL generates a 100MHz clock for the Nios II processor and othercontrollers. Four PIO pins are connected to the Micro SD Card socket. SD 4-bit Mode is used toaccess the Micro SD Card hardware.The SD 4-bit protocol and FAT File System function are allimplemented by Nios II software. The software is stored in the on-chip memory.DE0-CV User Manual52www.terasic.comJanuary 16, 2015Figure 5-6 Block diagram of the Micro SD demonstrationFigure 5-7 shows the software stack of this demonstration.

The Nios PIO block provides basic IOfunctions to access hardware directly. The functions are provided from Nios II system and thefunction prototype is defined in the header file <io.h>. The SD Card block implements 4-bit modeprotocol for communication with SD Cards. The FAT File System block implements readingfunction for FAT16 and FAT 32 file system. Long filename is supported.

By calling the public FATfunctions, users can browse files under the root directory of the MicroSD Card. Furthermore, userscan open a specific file and read the contents from the file. The main block implements maincontrol of this demonstration. When the program is executed, it detects whether an Micro SD Cardis inserted. If an MicroSD Card is found, it will check whether the MicroSD Card is formatted asFAT file system. If so, it searches all files in the root directory of the FAT file system and displaystheir names in the Nios II terminal. If a text file named “test.txt” is found, it will dump the filecontents.

If it successfully recognizes the FAT file system, it will turn on the LEDR4~LEDR0. Onthe other hand, it will turn on the LEDR9~LEDR5 if it fails to parse the FAT file system or if thereis no SD card found in the SD Card socket of the DE0-CV board. If users press KEY3 of theDE0-CV board, the program will perform the above process again.DE0-CV User Manual53www.terasic.comJanuary 16, 2015Figure 5-7 Software of micro SD demonstrationDesign Tools Quartus II14.0 Nios IIEclipse14.0Demonstration Source Code Quartus Project directory: DE0_CV_SD_DEMO Nios II Eclipse: DE0_CV_SD_DEMO\SoftwareNios II Project Compilation Before you attemptto compile the reference design under Nios II Eclipse, make sure the projectis cleaned firstby clicking ‘Clean’from the ‘Project’menu of Nios II Eclipse.Demonstration Batch FileDemo Batch File Folder:DE0_CV_SD_DEMO \demo_batchThe demo batch file includes following files:Batch Filefor USB-Blaster:DE0_CV_SD_DEMO.bat,DE0_CV_SD_DEMO.shFPGA Configure File: DE0_CV_SD_DEMO.sofNios II Program:DE0_CV_SD_DEMO.elfDE0-CV User Manual54www.terasic.comJanuary 16, 2015Demonstration SetupMake sure Quartus II and Nios II are installed on your PC.Power on the DE0-CV board.Connect USB Blaster to the DE0-CV board and install USB Blaster driver if necessary.Execute the demo batch file “DE0_CV_SD_DEMO.bat”for USB-Blaster II under the batch filefolder, DE0_CV_SD_DEMO\demo_batch After Nios II program is downloaded and executed successfully, a prompt message will bedisplayed in nios2-terminal. Copy DE0_CV_SD_DEMO\demo_batch\test.txt files to the root directory of the SD Card. Insert the Micro SD Card into the SD Card socket of DE0-CV, as shown in Figure 5-8.Figure 5-8 Insert the Micro SD card into DE0-CV Press KEY3of the DE0-CV board to start reading SD Card. The program will display SD Card information, as shown in Figure 5-9.DE0-CV User Manual55www.terasic.comJanuary 16, 2015Figure 5-9 Running result of SD_CARD demo on DE0-CV boardDE0-CV User Manual56www.terasic.comJanuary 16, 2015Additional InformationGetting HelpHere are the addresses where you can get help if you encounter problems: Terasic Inc.9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070.

TaiwanEmail: support@terasic.comWeb: www.terasic.comDE0-CV Web: www.DE0-CV.terasic.comRevision HistoryDateVersion2014.12First publicationDE0-CV User ManualChanges57www.terasic.comJanuary 16, 2015.

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