DE0_CV_User_Manual (1162586), страница 5

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1IntroductionThe DE0-CV System Builder is a Windows-based utility. It is designed to help users create aQuartus II project for DE0-CV within minutes. The generated Quartus II project files include:Quartus II project file (.qpf)Quartus II setting file (.qsf)Top-level design file (.v)Synopsis design constraints file (.sdc)Pin assignment document (.htm)The above files generated by the DE0-CV System Builder can also prevent occurrence of situationsthat are prone to compilation error when users manually edit the top-level design file or place pinassignment. The common mistakes that users encounter are: Board is damaged due to incorrect bank voltage setting or pin assignment. Board is malfunctioned because of wrong device chosen, declaration of pin location or directionis incorrect or forgotten. Performance degradation due to improper pin assignment.4.

2General Design FlowThis section provides an introduction to the design flow of building a Quartus II project forDE0-CV under the DE0-CV System Builder. The design flow is illustrated in Figure 4-1.The DE0-CV System Builder will generate two major files, a top-level design file (.v) and aQuartus II setting file (.qsf) after users launch the DE0-CV System Builder and create a new projectaccording to their design requirementsDE0-CV User Manual37www.terasic.comJanuary 16, 2015The top-level design file contains a top-level Verilog HDL wrapper for users to add their owndesign/logic.

The Quartus II setting file contains information such as FPGA device type, top-levelpin assignment, and the I/O standard for each user-defined I/O pin.Finally, the Quartus II programmer is used to download .sof file to the development board via JTAGinterface.Figure 4-1 Design flow of building a project from the beginning to the end4. 3Using DE0-CV System BuilderThis section provides the procedures in details on how to use the DE0-CV System Builder. Install and Launch the DE0-CV System BuilderThe DE0-CV System Builder is located in the directory: “Tools\SystemBuilder” of the DE0-CVSystem CD.

Users can copy the entire folder to a host computer without installing the utility. Awindow will pop up, as shown in Figure 4-2, after executing the DE0-CV SystemBuilder.exe on thehost computer.DE0-CV User Manual38www.terasic.comJanuary 16, 2015Figure 4-2 The GUI of DE0-CV System Builder Enter Project NameEnter the project name in the circled area, as shown in Figure 4-3.The project name typed in will be assigned automatically as the name of your top-level designentity.Figure 4-3 Enter the project nameDE0-CV User Manual39www.terasic.comJanuary 16, 2015 System ConfigurationUsers are given the flexibility in the System Configuration to include their choice of components inthe project, as shown in Figure 4-4. Each component onboard is listed and users can enable ordisable one or more components at will. If a component is enabled, the DE0-CV System Builderwill automatically generate its associated pin assignment, including the pin name, pin location, pindirection, and I/O standard.Figure 4-4 System configuration group GPIO ExpansionIf users connect any Terasic GPIO-based daughter card to the GPIO connector(s) on DE0-CV, theDE0-CV System Builder can generate a project that include the corresponding module, as shown inFigure 4-5.

It will also generate the associated pin assignment automatically, including pin name,pin location, pin direction, and I/O standard.DE0-CV User Manual40www.terasic.comJanuary 16, 2015Figure 4-5 GPIO expansion groupThe “Prefix Name” is an optional feature that denote the pin name of the daughter card assigned inyour design. Users may leave this field blank. Project Setting ManagementThe DE0-CV System Builder also provides the option to load a setting or save users’ current boardconfiguration in .cfg file, as shown in Figure 4-6.Figure 4-6 Project SettingsDE0-CV User Manual41www.terasic.comJanuary 16, 2015 Project GenerationWhen users press the Generate button as shown in Figure 4-7, the DE0-CV System Builder willgenerate the corresponding Quartus II files and documents, as listed in Table 4-1:Figure 4-7 Generate Quartus ProjectTable 4-1 Files generated by the DE0-CV System BuilderNo.1Filename<Project name>.vDescriptionTop level Verilog HDL file for Quartus II2<Project name>.qpfQuartus II Project File3<Project name>.qsfQuartus II Setting File4<Project name>.sdcSynopsis Design Constraints file for Quartus II5<Project name>.htmPin Assignment DocumentUsers can add custom logic into the project in Quartus II and compile the project to generate theSRAM Object File (.sof).DE0-CV User Manual42www.terasic.comJanuary 16, 2015Chapter 5Examples of AdvancedDemonstrationsThis chapter provides examples of advanced designs implemented by RTL or Qsys on the DE0-CVboard.

These reference designs cover the features of peripherals connected to the FPGA, such asPS/2, SDRAM, and SD card. All the associated files can be found in the directory \Demonstrationsof DE0-CV System CD. Installation of DemonstrationsTo install the demonstrations on your computer:Copy the folder Demonstrations to a local directory of your choice. It is important to make sure thepath to your local directory contains NO space. Otherwise it will lead to error in Nios II.Note : Quartus II v14.0 or later is required for all DE0-CV demonstrations to support Cyclone VFPGA device.5. 1 DE0-CV Factor y ConfigurationThe DE0-CV board has a default configuration bit-stream pre-programmed, which demonstratessome of the basic features onboard. The setup required for this demonstration and the location of itsfiles are shown below.Demonstration File Locations Project directory: DE0_CV_Default Bitstream used: DE0_CV_Default.sof ,DE0_CV_Default.pof or DE0_CV_Default.jicDemonstration Setup and InstructionsDE0-CV User Manual43www.terasic.comJanuary 16, 2015 Power on the DE0-CV board with the USB cable connected to the USB-Blaster port.

If necessary(that is, if the default factory configuration is not currently stored in the EPCS device), downloadthe bit stream to the board via JTAG interface. You should now be able to observe the 7-segment displays are showing a sequence of characters,and the red LEDs are blinking. Press FPGA_RESET to make LEDs and 7 SEGs all light on. If the VGA D-SUB connector is connected to a VGA display, it would show a color picture.Restore Factory Configuration Configuring the EPCS64 in AS Mode1.

Ensure that power is applied to the DE0_CV board.2. Connect the supplied USB cable to the USB Blaster port on the DE0-CV board3. Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW10) tothe PROG position.4. Execute the demo batch file “pof_DE0_CV_Default.bat” for USB-Blaster under the batchfile folder, DE0_CV_Default /demo_batch.5. Once the programming operation is finished, set the RUN/PROG slide switch back to theRUN position and then reset the board by turning the power switch off and back on; thisaction causes the new configuration data in the EPCS64 device to be loaded into the FPGAchip. Configuring the EPCS64 with .JIC File1.

Ensure that power is applied to the DE0_CV board.2. Connect the supplied USB cable to the USB Blaster port on the DE0-CV board.3. Execute the demo batch file “ DE0_CV_Default.bat” for USB-Blaster under the batch filefolder, DE0_CV_Default /demo_batch.4. As shown in Figure 5-1, It is able to not only load the bit stream into the FPGA in commandline, but also program or erase .jic file to the EPCS by executing the batch file.5. If users want to program a new design into the EPCS device, an easy method is to copy thenew .sof file (file name must be DE0_CV_Default.sof) into the demo_batch folder andexecute the DE0_CV_Default.bat. Option “2” will convert the .sof to .jic and option”3” willprogram .jic file into the EPCS device.DE0-CV User Manual44www.terasic.comJanuary 16, 2015Figure 5-1 Command line of the batch file to program the FPGA and EPCS device5.

2 SDRAM Test in Nios IIThere are many applications using SDRAM as a temporary storage. Both hardware and softwaredesigns are provided to illustrate how to perform memory access in Qsys in this demonstration. Italso shows how Altera’s SDRAM controller IP accesses SDRAM and how the Nios II processorreads and writes the SDRAM for hardware verification. The SDRAM controller handles complexaspects of accessing SDRAM such as initializing the memory device, managing SDRAM banks,and keeping the devices refreshed at certain interval. System Block DiagramFigure 5-2 shows the system block diagram of this demonstration. The system requires a 50 MHzclock input from the board. The SDRAM controller is configured as a 64MB controller.

Theworking frequency of the SDRAM controller is 143 MHz, and the Nios II program is running onthe on-chip memory.DE0-CV User Manual45www.terasic.comJanuary 16, 2015Figure 5-2 Block diagram of the SDRAM test in Nios IIThe system flow is controlled by a program running in Nios II. The Nios II program writes testpatterns into the entire 64MB of SDRAM first before calling the Nios II system function,alt_dcache_flush_all, to make sure all the data are written to the SDRAM.

It then reads data fromthe SDRAM for data verification. The program will show the progress in nios-terminal whenwriting/reading data to/from the SDRAM. When the verification process reaches 100%, the resultwill be displayed in nios-terminal.Design Tools Quartus II v14.0 Nios II Eclipse v14.0Demonstration Source Code Quartus project directory: DE0_CV_SDRAM_Nios_Test Nios II Eclipse directory: DE0_CV_SDRAM_Nios_Test \SoftwareNios II Project Compilation Click “Clean” from the “Project” menu of Nios II Eclipse before compiling the reference designin Nios II Eclipse.DE0-CV User Manual46www.terasic.comJanuary 16, 2015Demonstration Batch FileThe files are located in the director: \DE0_CV_SDRAM_Nios_Test \demo_batch.The folder includes the following files: Batch file for USB-Blaster II : DE0_CV_SDRAM_Nios_Test.bat andDE0_CV_SDRAM_Nios_Test.sh FPGA configuration file : DE0_CV_SDRAM_Nios_Test.sof Nios II program: DE0_CV_SDRAM_Nios_Test.elfDemonstration Setup Quartus II v14.0 and Nios II v14.0 must be pre-installed on the host PC. Power on the DE0_CV board. Connect the DE0_CV board (J13) to the host PC with a USB cable and install the USB-Blasterdriver if necessary. Execute the demo batch file “DE0_CV_SDRAM_Nios_Test.bat” from the directoryDE0_CV_SDRAM_Nios_Test\demo_batch After the program is downloaded and executed successfully, a prompt message will be displayedin nios2-terminal. Press any button (KEY3~KEY0) to start the SDRAM verification process.

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