DE0_CV_User_Manual (1162586), страница 4
Текст из файла (страница 4)
5 Using 2x20 GPIO Expansion HeadersThe board has two 40-pin expansion headers. Each header has 36 user pins connected directly to theCyclone V FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins.Both 5V and 3.3V can provide a total of 5W power.Each pin on the expansion headers is connected to two diodes and a resistor for protection againsthigh or low voltage level. Figure 3-11 shows the protection circuitry applied to all 2x36 data pins.Figure 3-11 shows the related schematics. Table 3-7 shows the pin assignment of two GPIOheaders.DE0-CV User Manual27www.terasic.comJanuary 16, 2015Figure 3-11 Connections between the GPIO header and Cyclone V FPGAFigure 3-12 I/O distribution of the expansion headersTable 3-7 Pin Assignment of Expansion HeadersSignal NameGPIO_0_D0GPIO_0_D1GPIO_0_D2GPIO_0_D3GPIO_0_D4GPIO_0_D5GPIO_0_D6DE0-CV User ManualFPGA Pin No.PIN_N16PIN_B16PIN_M16PIN_C16PIN_D17PIN_K20PIN_K2128DescriptionGPIO Connection 0[0]GPIO Connection 0[1]GPIO Connection 0[2]GPIO Connection 0[3]GPIO Connection 0[4]GPIO Connection 0[5]GPIO Connection 0[6]www.terasic.comJanuary 16, 2015GPIO_0_D7GPIO_0_D8GPIO_0_D9GPIO_0_D10GPIO_0_D11GPIO_0_D12GPIO_0_D13GPIO_0_D14GPIO_0_D15GPIO_0_D16GPIO_0_D17GPIO_0_D18GPIO_0_D19GPIO_0_D20GPIO_0_D21GPIO_0_D22GPIO_0_D23GPIO_0_D24GPIO_0_D25GPIO_0_D26GPIO_0_D27GPIO_0_D28GPIO_0_D29GPIO_0_D30GPIO_0_D31GPIO_0_D32GPIO_0_D33GPIO_0_D34GPIO_0_D35GPIO_1_D0GPIO_1_D1GPIO_1_D2GPIO_1_D3GPIO_1_D4GPIO_1_D5GPIO_1_D6GPIO_1_D7GPIO_1_D8GPIO_1_D9GPIO_1_D10GPIO_1_D11GPIO_1_D12GPIO_1_D13GPIO_1_D14GPIO_1_D15GPIO_1_D16GPIO_1_D17DE0-CV User ManualPIN_K22PIN_M20PIN_M21PIN_N21PIN_R22PIN_R21PIN_T22PIN_N20PIN_N19PIN_M22PIN_P19PIN_L22PIN_P17PIN_P16PIN_M18PIN_L18PIN_L17PIN_L19PIN_K17PIN_K19PIN_P18PIN_R15PIN_R17PIN_R16PIN_T20PIN_T19PIN_T18PIN_T17PIN_T15PIN_H16PIN_A12PIN_H15PIN_B12PIN_A13PIN_B13PIN_C13PIN_D13PIN_G18PIN_G17PIN_H18PIN_J18PIN_J19PIN_G11PIN_H10PIN_J11PIN_H14PIN_A1529GPIO Connection 0[7]GPIO Connection 0[8]GPIO Connection 0[9]GPIO Connection 0[10]GPIO Connection 0[11]GPIO Connection 0[12]GPIO Connection 0[13]GPIO Connection 0[14]GPIO Connection 0[15]GPIO Connection 0[16]GPIO Connection 0[17]GPIO Connection 0[18]GPIO Connection 0[19]GPIO Connection 0[20]GPIO Connection 0[21]GPIO Connection 0[22]GPIO Connection 0[23]GPIO Connection 0[24]GPIO Connection 0[25]GPIO Connection 0[26]GPIO Connection 0[27]GPIO Connection 0[28]GPIO Connection 0[29]GPIO Connection 0[30]GPIO Connection 0[31]GPIO Connection 0[32]GPIO Connection 0[33]GPIO Connection 0[34]GPIO Connection 0[35]GPIO Connection 1[0]GPIO Connection 1[1]GPIO Connection 1[2]GPIO Connection 1[3]GPIO Connection 1[4]GPIO Connection 1[5]GPIO Connection 1[6]GPIO Connection 1[7]GPIO Connection 1[8]GPIO Connection 1[9]GPIO Connection 1[10]GPIO Connection 1[11]GPIO Connection 1[12]GPIO Connection 1[13]GPIO Connection 1[14]GPIO Connection 1[15]GPIO Connection 1[16]GPIO Connection 1[17]www.terasic.comJanuary 16, 2015GPIO_1_D18GPIO_1_D19GPIO_1_D20GPIO_1_D21GPIO_1_D22GPIO_1_D23GPIO_1_D24GPIO_1_D25GPIO_1_D26GPIO_1_D27GPIO_1_D28GPIO_1_D29GPIO_1_D30GPIO_1_D31GPIO_1_D32GPIO_1_D33GPIO_1_D34GPIO_1_D35PIN_J13PIN_L8PIN_A14PIN_B15PIN_C15PIN_E14PIN_E15PIN_E16PIN_F14PIN_F15PIN_F13PIN_F12PIN_G16PIN_G15PIN_G13PIN_G12PIN_J17PIN_K16GPIO Connection 1[18]GPIO Connection 1[19]GPIO Connection 1[20]GPIO Connection 1[21]GPIO Connection 1[22]GPIO Connection 1[23]GPIO Connection 1[24]GPIO Connection 1[25]GPIO Connection 1[26]GPIO Connection 1[27]GPIO Connection 1[28]GPIO Connection 1[29]GPIO Connection 1[30]GPIO Connection 1[31]GPIO Connection 1[32]GPIO Connection 1[33]GPIO Connection 1[34]GPIO Connection 1[35]3.
6 Using VGAThe DE0-CV board includes a 16-pin D-SUB connector for VGA output. The VGA synchronizationsignals are provided directly from the Cyclone V FPGA, and a 4-bit DAC using resistor network isused to produce the analog data signals (red, green, and blue). The associated schematic is given inFigure 3-13 and can support standard VGA resolution (640x480 pixels, at 25 MHz).Figure 3-13 Connections between the FPGA and VGADE0-CV User Manual30www.terasic.comJanuary 16, 2015The timing specification for VGA synchronization and RGB (red, green, blue) data can be easilyfound on website nowadays.
Figure 3-13 illustrates the basic timing requirements for each row(horizontal) displayed on a VGA monitor. An active-low pulse of specific duration is applied to thehorizontal synchronization (hsync) input of the monitor, which signifies the end of one row of dataand the start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for atime period called the back porch (b) after the hsync pulse occurs, which is followed by the displayinterval (c). During the data display interval the RGB data drives each pixel in turn across the rowbeing displayed.
Finally, there is a time period called the front porch (d) where the RGB signalsmust again be off before the next hsync pulse can occur. The timing of vertical synchronization(vsync) is similar to the one shown in Figure 3-14, except that a vsync pulse signifies the end ofone frame and the start of the next, and the data refers to the set of rows in the frame (horizontaltiming). Table 3-8 and Table 3-9 show different resolutions and durations of time period a, b, c, andd for both horizontal and vertical timing.The pin assignments between the Cyclone V FPGA and the VGA connector are listed in Table3-10.Figure 3-14 VGA horizontal timing specificationTable 3-8 VGA Horizontal Timing SpecificationVGA modeConfigurationVGA(60Hz)Horizontal Timing SpecResolution(HxV)640x480a(pixelb(pixelc(pixeld(pixelclockclockclockclockcycle)96cycle)48cycle)640cycle)16Pixel clock(MHz)25Table 3-9 VGA Vertical Timing SpecificationVGA modeConfigurationVGA(60Hz)Vertical Timing SpecResolution(HxV)640x480DE0-CV User Manuala(lines)231b(lines)33c(lines)480d(lines)10Pixel clock(MHz)25www.terasic.comJanuary 16, 2015Table 3-10 Pin Assignment of VGASignal NameFPGA Pin No.DescriptionVGA_R0PIN_A9VGA Red[0]VGA_R1PIN_B10VGA Red[1]VGA_R2PIN_C9VGA Red[2]VGA_R3PIN_A5VGA Red[3]VGA_G0PIN_L7VGA Green[0]VGA_G1PIN_K7VGA Green[1]VGA_G2PIN_J7VGA Green[2]VGA_G3PIN_J8VGA Green[3]VGA_B0VGA_B1VGA_B2VGA_B3VGA_HSVGA_VSPIN_B6PIN_B7PIN_A8PIN_A7PIN_H8PIN_G8VGA Blue[0]VGA Blue[1]VGA Blue[2]VGA Blue[3]VGA H_SYNCVGA V_SYNC3.
7 PS/2 Serial Por tThe DE0-CV board comes with a standard PS/2 interface and a connector for a PS/2 keyboard ormouse. Figure 3-15 shows the connection of PS/2 circuit to the FPGA. Users can use the PS/2keyboard and mouse on the DE0-CV board simultaneously by a PS/2 Y-Cable, as shown in Figure3-16. Instructions on how to use PS/2 mouse and/or keyboard can be found on various educationalwebsites.
The pin assignment associated to this interface is shown in Table 3-11.Note: If users connect only one PS/2 equipment, the PS/2 signals connected to the FPGA I/O shouldbe “PS2_CLK” and “PS2_DAT”.Figure 3-15 Connections between the FPGA and PS/2DE0-CV User Manual32www.terasic.comJanuary 16, 2015Figure 3-16 Y-Cable for using keyboard and mouse simultaneouslyTable 3-11 Pin Assignment of PS/2Signal NamePS2_CLKPS2_DATPS2_CLK2PS2_DAT2FPGA Pin No.PIN_D3PIN_G2PIN_E2PIN_G1DescriptionPS/2 ClockPS/2 DataPS/2 Clock (reserved for second PS/2 device)PS/2 Data (reserved for second PS/2 device)3. 8 Micro SD-Card SocketThe development board supports Micro SD card interface using x4 data lines.
Figure 3-17 showsthe related signals connections between the SD Card and Cyclone V FPGA and Figure 3-18 showsmicro SD card plug-in position.Finally, Table 3-12 lists all the associated pins.Figure 3-17 Connection between the SD Card Socket and Cyclone V FPGADE0-CV User Manual33www.terasic.comJanuary 16, 2015Figure 3-18 Micro SD CardTable 3-12 Pin Assignment of Micro SD Card SocketSignal NameSD_CLKSD_CMDSD_DATA0SD_DATA1SD_DATA2SD_DATA3FPGA Pin No.PIN_H11PIN_B11PIN_K9PIN_D12PIN_E12PIN_C11DescriptionSerial ClockCommand, ResponseSerial Data 0Serial Data 1Serial Data 2Serial Data 33. 9 Using SDRAMThe board features 64MB of SDRAM with a single 64MB (32Mx16) SDRAM chip.
The chipconsists of 16-bit data line, control line, and address line connected to the FPGA. This chip uses the3.3V LVCMOS signaling standard. Connections between the FPGA and SDRAM are shown inFigure 3-19, and the pin assignment is listed in Table 3-13.DE0-CV User Manual34www.terasic.comJanuary 16, 2015Figure 3-19 Connections between the FPGA and SDRAMTable 3-13 Pin Assignment of SDRAMSignal NameDRAM_ADDR0FPGA Pin No.DescriptionPIN_W8SDRAM Address[0]DRAM_ADDR1PIN_T8SDRAM Address[1]DRAM_ADDR2PIN_U11SDRAM Address[2]DRAM_ADDR3PIN_Y10SDRAM Address[3]DRAM_ADDR4PIN_N6SDRAM Address[4]DRAM_ADDR5PIN_AB10SDRAM Address[5]DRAM_ADDR6PIN_P12SDRAM Address[6]DRAM_ADDR7PIN_P7SDRAM Address[7]DRAM_ADDR8PIN_P8SDRAM Address[8]DRAM_ADDR9PIN_R5SDRAM Address[9]DRAM_ADDR10PIN_U8SDRAM Address[10]DRAM_ADDR11PIN_P6SDRAM Address[11]DRAM_ADDR12PIN_R7SDRAM Address[12]DRAM_DQ0PIN_Y9SDRAM Data[0]DRAM_DQ1PIN_T10SDRAM Data[1]DRAM_DQ2PIN_R9SDRAM Data[2]DRAM_DQ3PIN_Y11SDRAM Data[3]DRAM_DQ4PIN_R10SDRAM Data[4]DRAM_DQ5PIN_R11SDRAM Data[5]DRAM_DQ6PIN_R12SDRAM Data[6]DRAM_DQ7PIN_AA12SDRAM Data[7]DRAM_DQ8PIN_AA9SDRAM Data[8]DRAM_DQ9PIN_AB8SDRAM Data[9]DE0-CV User Manual35www.terasic.comJanuary 16, 2015DRAM_DQ10PIN_AA8SDRAM Data[10]DRAM_DQ11PIN_AA7SDRAM Data[11]DRAM_DQ12PIN_V10SDRAM Data[12]DRAM_DQ13PIN_V9SDRAM Data[13]DRAM_DQ14PIN_U10SDRAM Data[14]DRAM_DQ15PIN_T9SDRAM Data[15]DRAM_BA0PIN_T7SDRAM Bank Address[0]DRAM_BA1PIN_AB7SDRAM Bank Address[1]DRAM_LDQMPIN_U12SDRAM byte Data Mask[0]DRAM_UDQMPIN_N8SDRAM byte Data Mask[1]DRAM_RAS_NPIN_AB6SDRAM Row Address StrobeDRAM_CAS_NPIN_V6SDRAM Column Address StrobeDRAM_CKEPIN_R6SDRAM Clock EnableDRAM_CLKPIN_AB11SDRAM ClockDRAM_WE_NPIN_AB5SDRAM Write EnableDRAM_CS_NPIN_U6SDRAM Chip SelectDE0-CV User Manual36www.terasic.comJanuary 16, 2015Chapter 4DE0-CV System BuilderThis chapter describes how users can create a custom design project with the tool named DE0-CVSystem Builder.4.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
