DE0_CV_User_Manual (1162586), страница 3

Просмтор этого файла доступен только зарегистрированным пользователям. Но у нас супер быстрая регистрация: достаточно только электронной почты!

Текст из файла (страница 3)

1 Configuration of Cyclone V FPGA on DE0-CVThe DE0-CV board contains a serial configuration device that stores configuration data for theCyclone V FPGA. This configuration data is automatically loaded from the configuration deviceinto the FPGA when powered on. Using the Quartus II software, it is possible to reconfigure theFPGA at any time, and it is also possible to change the non-volatile data that is stored in the serialconfiguration device. Both types of programming methods are described below.1.

JTAG programming: In this method of programming, named after the IEEE standards Joint TestAction Group, the configuration bit stream is downloaded directly into the Cyclone V FPGA. TheFPGA will retain this configuration as long as power is applied to the board; the configurationinformation will be lost when the power is turned off.2. AS programming: In this method, called Active Serial programming, the configuration bitstream is downloaded into the Altera EPCS64 serial configuration device. It provides non-volatilestorage of the bit stream, so that the information is retained even when the power supply to theDE0-CV board is turned off.

When the board’s power is turned on, the configuration data in theEPCS64 device is automatically loaded into the Cyclone V FPGA.The sections below describe the steps to perform both JTAG and AS programming. For bothmethods the DE0-CV board is connected to a host computer via a USB cable. Using this connection,the board will be identified by the host computer as an Altera USB Blaster device.DE0-CV User Manual18www.terasic.comJanuary 16, 2015 Configuring the FPGA in JTAG ModeFigure 3-1 illustrates the JTAG configuration setup. To download a configuration bit stream intothe Cyclone V FPGA, you need to perform the following steps: Ensure that power is applied to the DE0-CV board Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW10) to theRUN position (See Figure 3-2) Connect the USB cable provided to the USB Blaster port on the DE0-CV board The FPGA can now be programmed by using the Quartus II Programmer to select aconfiguration bit stream file with the .sof filename extensionFigure 3-1Figure 3-2The JTAG configuration schemeThe RUN/PROG switch (SW10) is set in JTAG modeDE0-CV User Manual19www.terasic.comJanuary 16, 2015 Configuring the EPCS64 in AS ModeFigure 3-3 illustrates the AS configuration setup.

To download a configuration bit stream into theEPCS64 serial configuration device, you need to perform the following steps: Ensure that power is applied to the DE0-CV board. Connect the USB cable provided to the USB Blaster port on the DE0-CV board Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW10) to thePROG position. The EPCS64 chip can now be programmed by using the Quartus II Programmer to select aconfiguration bit stream file with the .pof filename extension. Once the programming operation is finished, set the RUN/PROG slide switch back to the RUNposition and then reset the board by turning the power switch off and back on; this action causesthe new configuration data in the EPCS64 device to be loaded into the FPGA chip.Figure 3-3DE0-CV User ManualThe AS configuration scheme20www.terasic.comJanuary 16, 2015 Status LED The FPGA development board includes board-specific status LEDs to indicate board status.Please refer to Table 3-1 for the description of the LED indicator.

Please refer to Figure 3-4 fordetailed LED location.Table 3-1 Status LEDBoardLED NameDescriptionD153.3-V PowerIlluminates when 3.3-V power is active.D16ULEDIlluminates when the on-board USB-Blaster is workingReferenceFigure 3-4 Status LED position3. 2 Using the LEDs and Switches User-Defined Push-buttonsThe board includes four user defined push-buttons and one FPGA reset button that allow users tointeract with the Cyclone V device as shown in Figure 3-5. Each of these switches is debouncedusing a Schmitt Trigger circuit, as indicated in Figure 3-6. The five outputs called KEY0, KEY1,DE0-CV User Manual21www.terasic.comJanuary 16, 2015KEY2, KEY3 and RESET_N of the Schmitt Trigger devices are connected directly to the CycloneV FPGA. Each push-button switch provides a high logic level when it is not pressed, and provides alow logic level when depressed. Since the push-button switches are debounced, they are appropriatefor using as clocks or reset inputs in a circuit.Figure 3-5 Connections between the push-button and Cyclone V FPGAPushbutton depressedPushbutton releasedBeforeDebouncingSchmitt TriggerDebouncedFigure 3-6Switch debouncing User-Defined Slide SwitchThere are ten slide switches connected to FPGA on the board (See Figure 3-7).

These switches arenot debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch isconnected directly to a pin on the Cyclone V FPGA. When the switch is in the DOWN position(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch isin the UP position it provides a high logic level.DE0-CV User Manual22www.terasic.comJanuary 16, 2015Figure 3-7Connections between the slide switches and Cyclone V FPGA User-Defined LEDsThere are also ten user-controllable LEDs connected to FPGA on the board.

Each LED is drivendirectly by a pin on the Cyclone V FPGA; driving its associated pin to a high logic level turns theLED on, and driving the pin low turns it off. Figure 3-8 shows the connections between LEDs andCyclone V FPGA. Table 3-2, Table 3-3 and Table 3-4 list the pin assignment of user push-buttons,switches, and LEDs.DE0-CV User Manual23www.terasic.comJanuary 16, 2015Figure 3-8Connections between the LEDs and Cyclone V FPGATable 3-2 Pin Assignment of Push-buttonsSignal NameKEY0KEY1KEY2KEY3RESET_NFPGA Pin No.PIN_U7PIN_W9PIN_M7PIN_M6PIN_P22DescriptionPush-button[0]Push-button[1]Push-button[2]Push-button[3]Push-button which connectedto DEV_CLRN Pin of FPGATable 3-3 Pin Assignment of Slide SwitchesSignal NameSW0SW1SW2SW3SW4SW5SW6SW7SW8SW9DE0-CV User ManualFPGA Pin No.PIN_U13PIN_V13PIN_T13PIN_T12PIN_AA15PIN_AB15PIN_AA14PIN_AA13PIN_AB13PIN_AB1224DescriptionSlide Switch[0]Slide Switch[1]Slide Switch[2]Slide Switch[3]Slide Switch[4]Slide Switch[5]Slide Switch[6]Slide Switch[7]Slide Switch[8]Slide Switch[9]www.terasic.comJanuary 16, 2015Table 3-4 Pin Assignment of LEDsSignal NameLEDR0LEDR1LEDR2LEDR3LEDR4LEDR5LEDR6LEDR7LEDR8LEDR9FPGA Pin No.PIN_AA2PIN_AA1PIN_W2PIN_Y3PIN_N2PIN_N1PIN_U2PIN_U1PIN_L2PIN_L1DescriptionLED [0]LED [1]LED [2]LED [3]LED [4]LED [5]LED [6]LED [7]LED [8]LED [9]3.

3 Using the 7-segment DisplaysThe DE0-CV board has six 7-segment displays. These displays are paired to display numbers invarious sizes. Figure 3-9 shows the connection of seven segments (common anode) to pins onCyclone V FPGA. The segment can be turned on or off by applying a low logic level or high logiclevel from the FPGA, respectively.Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure 3-9.Table 3-5 shows the pin assignment of FPGA to the 7-segment displays.Figure 3-9 Connections between the 7-segment display HEX0 and the Cyclone V FPGATable 3-5 Pin Assignment of 7-segment DisplaysSignal NameHEX00HEX01DE0-CV User ManualFPGA Pin No.PIN_U21PIN_V2125DescriptionSeven Segment Digit 0[0]Seven Segment Digit 0[1]www.terasic.comJanuary 16, 2015HEX02HEX03HEX04HEX05HEX06HEX10HEX11HEX12HEX13HEX14HEX15HEX16HEX20HEX21HEX22HEX23HEX24HEX25HEX26HEX30HEX31HEX32HEX33HEX34HEX35HEX36HEX40HEX41HEX42HEX43HEX44HEX45HEX46HEX50HEX51HEX52HEX53HEX54HEX55HEX56DE0-CV User ManualPIN_W22PIN_W21PIN_Y22PIN_Y21PIN_AA22PIN_AA20PIN_AB20PIN_AA19PIN_AA18PIN_AB18PIN_AA17PIN_U22PIN_Y19PIN_AB17PIN_AA10PIN_Y14PIN_V14PIN_AB22PIN_AB21PIN_Y16PIN_W16PIN_Y17PIN_V16PIN_U17PIN_V18PIN_V19PIN_U20PIN_Y20PIN_V20PIN_U16PIN_U15PIN_Y15PIN_P9PIN_N9PIN_M8PIN_T14PIN_P14PIN_C1PIN_C2PIN_W1926Seven Segment Digit 0[2]Seven Segment Digit 0[3]Seven Segment Digit 0[4]Seven Segment Digit 0[5]Seven Segment Digit 0[6]Seven Segment Digit 1[0]Seven Segment Digit 1[1]Seven Segment Digit 1[2]Seven Segment Digit 1[3]Seven Segment Digit 1[4]Seven Segment Digit 1[5]Seven Segment Digit 1[6]Seven Segment Digit 2[0]Seven Segment Digit 2[1]Seven Segment Digit 2[2]Seven Segment Digit 2[3]Seven Segment Digit 2[4]Seven Segment Digit 2[5]Seven Segment Digit 2[6]Seven Segment Digit 3[0]Seven Segment Digit 3[1]Seven Segment Digit 3[2]Seven Segment Digit 3[3]Seven Segment Digit 3[4]Seven Segment Digit 3[5]Seven Segment Digit 3[6]Seven Segment Digit 4[0]Seven Segment Digit 4[1]Seven Segment Digit 4[2]Seven Segment Digit 4[3]Seven Segment Digit 4[4]Seven Segment Digit 4[5]Seven Segment Digit 4[6]Seven Segment Digit 5[0]Seven Segment Digit 5[1]Seven Segment Digit 5[2]Seven Segment Digit 5[3]Seven Segment Digit 5[4]Seven Segment Digit 5[5]Seven Segment Digit 5[6]www.terasic.comJanuary 16, 20153.

4 Clock Circuitr yFigure 3-10 shows the clock circuit of DE0-CV Board, the crystal 50 MHz buffered to four 50MHzclock. The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3-6.Figure 3-10 Clock circuit of the FPGA BoardTable 3-6 Pin Assignment of Clock InputsSignal NameCLOCK_50CLOCK2_50CLOCK3_50CLOCK4_50FPGA Pin No.PIN_M9PIN_H13PIN_E10PIN_V15Description50 MHz clock input(Bank 3B)50 MHz clock input(Bank 7A)50 MHz clock input(Bank 8A)50 MHz clock input(Bank 4A)3.

Характеристики

Список файлов семинаров