Диссертация (1143817), страница 18
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На основе полученных результатовсформулирована методика параметрического синтеза ЦАП на источниках тока.5.Проведён обзор известных способов компенсации систематической ошибки.Установлены факторы, влияющие на снижение уровня DNL и INL. Данырекомендации по выбору методики компенсации систематической ошибки взависимости от разрядности ЦАП. Отмечено, что известные методики пригодны дляЦАП на источниках тока, но не могут применяться для резистивных унарных ЦАП.140На основе выявленных закономерностей предложена методика расстановки«шахматный конь», позволяющая снизить INL резистивного ЦАП.6.Для проверки эффективности предложеннойметодики «шахматный конь»разработан 10-ти разрядный сегментный резистивный ЦАП и тестовая микросхема.Тестовая микросхема содержит два ЦАП с различной топологией массивавзвешивающих элементов: один ЦАП без компенсации, другой – с компенсацией попредложенной методике.
Проведённые измерения показали, что предложеннаяметодика позволила в среднем на 20% снизить как максимальную, так и среднююINL в диапазоне рабочих температур от –40 °C до +85 °C.Таким образом, представленные в работе задачи выполнены, цель работыдостигнута.141Список литературы1.1.W. Kester. Data Conversion Handbook.
Elsevier: Oxford, 2005.1.2.R. Kubokawa, T. Ohshima, A. Tomar, P. Ramesh, H. Kanaya, K. Yoshida. Development oflow power DAC with pseudo Fibonacci sequence / IEEE Asia Pacific Conference onCircuits and Systems (APCCAS), 2010, pp. 370–373.1.3.K. Hokazono, D. Kanemoto, R. Pokharel, A. Tomar, H. Kanaya, K.Yoshida. A low-glitchand small-logic-area Fibonacci Series DAC / IEEE 54th International MidwestSymposium on Circuits and Systems (MWSCAS), 2011, pp. 1–4.1.4.J.
Schoeff. An inherently monotonic 12 bit DAC / IEEE Journal of Solid-State Circuits,1979, vol. 14, no 6, pp 904–911.1.5.Д. В. Морозов, М. С. Енученко. Цифро-аналоговые преобразователи с унарной исегментнойархитектурами/Научно-техническиеведомостиСПбГПУИнформатика.
Телекоммуникации. Управление, 1 (164), 2013, с. 81–86.1.6.R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation, 3rd ed. IEEE Press:Piscataway, 2010.1.7.A. Van den Bosch, M. S. J. Steyaert, W. Sansen. Static and dynamic performancelimitations for high speed D/A converters. Springer Science+Business: New York, 2004.1.8.L. Cong. Pseudo C-2C ladder-based data converter technique / IEEE Transactions onCircuits and Systems II: Analog and Digital Signal Processing, 2001, vol. 48, no. 10, pp.927–929.1.9.D.
Marche, Y. Savaria. Modeling R−2R Segmented-Ladder DACs / IEEE Transactions onCircuits and Systems I: Regular Papers, 2010, vol. 57, no. 1, pp. 31–43.1.10.Y. Li, T. Zeng, D. Chen. A high resolution and high accuracy R-2R DAC based on orderedelement matching / IEEE International Symposium on Circuits and Systems (ISCAS),2013, pp. 1974–1977.1.11.C.-C. Chen, N.-K. Lu. Nonlinearity analysis of R-2R ladder-based current-steering digitalto analog converter / IEEE International Symposium on Circuits and Systems (ISCAS),2013, pp.
833–836.1421.12.W. Guo, T. Abraham, S. Chiang, C. Trehan, M. Yoshioka, N. Sun. An Area and PowerEfficient Iref Compensation Technique for Voltage-Mode R-2R DACs / IEEETransactions on Circuits and Systems II: Express Briefs, 2015, vol. PP, no. 99, pp. 1–5.1.13.F. Burcea, H. Habal, H. E. Graeb. A New Chessboard Placement and Sizing Method forCapacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity / IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, vol.35, no. 9, pp. 1397–1410.1.14.M.
A. M. Sodagar, R. Mohammadi, P. Adl. A novel multi-step C-2C DAC architecture /19th IEEE International Conference on Electronics, Circuits, and Systems, 2012, pp. 189–192.1.15.C. Zhou, Z. Tao. A high accuracy DAC designed with low offset follower structure / IEEEInformation Technology, Networking, Electronic and Automation Control Conference,2016, pp. 356–360.1.16.K.
Bult, G. J. G. M. Geelen. An inherently linear and compact MOST-only current divisiontechnique / IEEE Journal of Solid-State Circuits, 1992, vol. 27, no. 12, pp. 1730–1735.1.17.H. Fei, R. Geiger. Linear Current Division Principles / IEEE International Symposium onCircuits and Systems, 2007, pp. 2830–2833.1.18.L. Wang, Y. Fukatsu, K. Watanabe.
Characterization of current-mode CMOS R-2R ladderdigital-to-analog converters / IEEE Transactions on Instrumentation and Measurement,2001, vol. 50, no. 6, pp. 1781–1786.1.19.C.-Y. Chen, C.-J. Cheng, C.-C. Yu. Design of current-mode digital-to-analog converterin hybrid architecture / The 3rd International IEEE-NEWCAS Conference, 2005, pp. 231–234.1.20.D. Karadimas, M. Papamichail, K. Efstathiou.
A MOST-Only R-2R ladder-basedarchitecture for high linearity DACs / 4th European Conference on Circuits and Systemsfor Communications (ECCSC), 2008, pp. 158–161.1.21.H. Klimach; M. Schneider; C. Galup-Montoro. An M-2M digital-to-analog converterdesign methodology based on a physical mismatch model / IEEE InternationalSymposium on Circuits and Systems, 2008, pp. 2254–2257.1431.22.T.-C. Lee, C.-H.
Lin. Nonlinear R-2R Transistor-Only DAC / IEEE Transactions on Circuitsand Systems I: Regular Papers, 2010, vol. 57, no. 10, pp. 2644–2653.1.23.D. Arbet, G. Nagy, V. Stopjakova, G. Gyepes. A self-calibrated binary weighted DAC in90nm CMOS technology / 29th International Conference on MicroelectronicsProceedings (MIEL), 2014, pp. 383–386.1.24.G.
Serrano, M. Kucic, P. Hasler. Investigating programmable floating-gate digital-toanalog converter as single element or element arrays / The 2002 45th MidwestSymposium on Circuits and Systems, 2002, vol. 1, pp. I-75-7.1.25.G. Serrano, P. Hasler. A floating gate DAC array, ISCAS '04 Proceedings of theInternational Symposium on Circuits and Systems, 2004, vol. 1, pp.
I-357-I-360.1.26.E. Ozalevli, P. Hasler, F. Adil. Programmable voltage-output, floating-gate digitalanalog converter / Proceedings of the 2004 International Symposium on Circuits andSystems, 2004, vol. 1, pp. I-1064-7.1.27.E. Ozalevli, C. M.
Twigg, P. Hasler. 10-bit programmable voltage-output digital-analogconverter / IEEE International Symposium on Circuits and Systems, 2005, vol. 6, pp.5553–5556.1.28.E. Ozalevli, Haw-Jing Lo, P. E. Hasler. Binary-Weighted Digital-to-Analog ConverterDesign Using Floating-Gate Voltage References / IEEE Transactions on Circuits andSystems I: Regular Papers, 2008, vol. 55, no. 4, pp.
990–998.1.29.Dongwon Seo. A Heterogeneous 16-Bit DAC Using a Replica Compensation / IEEETransactions on Circuits and Systems I: Regular Papers, 2008, vol. 55, no. 6, pp. 1455–1463.1.30.C. Chuen-Yau, C. Chi-Jung, Y. Chien-Cheng. Design of current-mode digital-to-analogconverter in hybrid architecture / The 3rd International IEEE-NEWCAS Conference,2005, pp. 231–234.1.31.M. S. Yenuchenko. Thermometric decoders for high resolution digital-to-analogconverters / IEEE NW Russia Young Researchers in Electrical and Electronic EngineeringConference (EIConRusNW), 2016, pp. 379–384.1.32.D. Yao, Y. Sun, M. Higashino, S.
Nizam Mohyar, T. Yanagida, T. Arafune, N. Tsukiji, H.Kobayashi. DAC linearity improvement with layout technique using magic and latin144squares / 2017 International Symposium on Intelligent Signal Processing andCommunication Systems (ISPACS), 2017, pp. 616–621.1.33.M. Nazari, L. Sharifi, A. Aghajani, O. Hashemipour. A 12-bit high performance currentsteering DAC using a new binary to thermometer decoder / 2016 24th IranianConference on Electrical Engineering (ICEE), 2016, pp. 1919–1924.1.34.B.
Liu, Y. Wang, G. Guo, Song Jia, Xing Zhang. A novel dynamic element matchtechnique in current-steering DAC / 2013 IEEE 10th International Conference on ASIC,2013, pp. 1–4.1.35.X. Li; Q. Wei, H. Yang. Code-independent output impedance: A new approach toincreasing the linearity of current-steering DACs / 2011 18th IEEE InternationalConference on Electronics, Circuits, and Systems, 2011, pp. 216–219.1.36.W.-T. Lin, T.-H. Kuo.
A Compact Dynamic-Performance-Improved Current-SteeringDAC With Random Rotation-Based Binary-Weighted Selection / IEEE Journal of SolidState Circuits, 2012, vol. 47, no. 2, pp. 444–453.2.1.V. Shen, D. Hodges. A 60ns glitch free NMOS DAC / IEEE International Solid-StateCircuits Conference. Digest of Technical Papers, 1983, vol. XXVI, pp. 188–189.2.2.T. Miki, Y. Nakamura, M. Nakaya, S.
Asai, Y. Akasaka, Y. Horiba. An 80-MHz 8-bit CMOSD/A converter / IEEE Journal of Solid-State Circuits, 1986, vol. 21, no. 6, pp. 983–988.2.3.K. Kyaw, R. L. Geiger. Multi-dimensional approach to high resolution and high speedbinary-to-thermometer decoding / Proceedings. The 16th International Conference onMicroelectronics, 2004, pp. 509–512.2.4.P. Aliparast, N. Nasirzadeh. Very high-speed and high-accuracy current-steering CMOSD/A converter using a novel 3-D decoder / Analog Integrated Circuits and SignalProcessing, 2009, vol.
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