Диссертация (1143817), страница 19
Текст из файла (страница 19)
60, pp. 195–204.2.5.P. Aliparast, Z. D. Koozehkanai, J. Sobhi, N. Nasirzadeh, B. A. Soltany. Design of a 10-bitlow power current-steering digital-to-analog converter based on a 4-D thermometerdecoding matrix / Proceedings of the 17th International Conference Mixed Design ofIntegrated Circuits and Systems, 2010, pp. 243–246.1452.6.Van Der Plas, A. M. Geert, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, G. G. E. Gielen.A 14-bit intrinsic accuracy Q2 random walk CMOS DAC / IEEE Journal of Solid-StateCircuits, 1999, vol. 34, no.
12, pp. 1708–1718.2.7.P. Palmers, M. Steyaert. A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a5-bit 1GS/s core in 130nm / 34th European Solid State Circuits Conference (ESSCIRC),2008, pp. 214-217.2.8.P. Palmers, M. S. J. Steyaert. A 10–Bit 1.6-GS/s 27-mW Current Steering D/A ConverterWith 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS / IEEE Transactions on Circuitsand Systems I: Regular Papers, 2010, vol. 57, no. 11, pp.
2870–2879.2.9.A. Van den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J.Bastos, M. Steyaert, G. Gielen, W. Sansen. A 12 bit 200 MHz low glitch CMOS D/Aconverter / Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998,pp. 249–252.2.10.M. S. Enuchenko, D. V.
Morozov, M. M. Pilipko. An 8-bit Parallel DAC with SegmentedArchitecture / Journal of Communications Technology and Electronics, 2017, vol. 62,no. 1, pp. 89–100.3.1.P. Hendriks. Specifying communication DACs / IEEE Spectrum, vol. 34, pp. 58–69, July1997.3.2.M. S. O. Alink, A. B. J. Kokkeler, E. A. M. Klumperink, K.
C. Rovers, G. J. M. Smit, B. Nauta.Spurious-Free Dynamic Range of a Uniform Quantizer / IEEE Transactions on Circuitsand Systems II: Express Briefs, 2009, vol. 56, no. 6, pp. 434–438.3.3.N. Ghittori, A. Vigna, P. Malcovati. Analysis of the ideal SFDR limit for an N bit digitalto-analog converter / 12th IEEE International Conference on Electronics, Circuits andSystems, 2005, pp. 1–4.4.1.A.
V. den Bosch, M. Steyaert, W. Sansen. SFDR-bandwidth limitations for high-speedhigh-resolution current-steering CMOS D/A converters / In Proc. IEEE ICECS, 1999, vol.3, pp. 1193–1196.1464.2.S. Luschas, H.-S. Lee. Output impedance requirements for DACs / Proc. IEEE Int. Symp.Circuit and Systems (ISCAS), vol. 1, pp.
1-861–1-864, May 2003.4.3.P. Palmers, M. Steyeart. A 11 mW 68 dB SFDR 100 MHz bandwidth SD-DAC based ona 5-bit 1 GS/s core in 130 nm / in Proc. ESSCIRC, Sep. 2008, pp. 214–217.4.4.C.-H. Lin, F. M. L. van der Goes, J. R. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu,K. Bult. A 12 bit 2.9 GS/s DAC with IM3 < -60 dBc beyond 1 GHz in 65 nm CMOS / IEEEJournal of Solid-State Circuits, vol. 44, no.
12, Dec. 2009, pp. 3285—3293.4.5.W.-H. Tseng, C.-W. Fan, J.-T. Wu. A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With>70 dBSFDR up to 500 MHz / IEEE Journal of Solid-State Circuits, 2011, vol. 46, no. 12, pp.2845–2856.4.6.N. Pal, P. Nandi, R. Biswas, A. G. Katakwar. Placement-Based Nonlinearity ReductionTechnique for Differential Current-Steering DAC / IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, 2016, vol. 24, no. 1, pp. 233–242.4.7.S. M. McDonnell, V. J.
Patel, Luke Duncan, Brian Dupaix, Waleed Khalil. Compensationand Calibration Techniques for Current-Steering DACs / IEEE Circuits and SystemsMagazine, 2017, vol. 17, no. 2, pp. 4–26.4.8.J. Bastos, A. M. Marques, M.S.J. Steyaert, W. Sansen. A 12-Bit Intrinsic Accuracy HighSpeed CMOS DAC / IEEE Journal of Solid-State Circuits, vol. 33, no.
12, pp. 1959–1969,Dec. 1998.4.9.M. Clara; A. Wiesbauer; W. Klatzer. Nonlinear distortion in current-steering D/Aconverters due to asymmetrical switching errors / IEEE International Symposium onCircuits and Systems, 2004, vol. 1, pp. I-285–I-288.4.10.K. O. Andersson; M. Vesterbacka. Modeling of glitches due to rise/fall asymmetry incurrent-steering digital-to-analog converters / IEEE Transactions on Circuits andSystems I: Regular Papers, 2005, vol. 52, no. 11, pp. 2265–2275.4.11.D. A. Mercer. Low-Power Approaches to High-Speed Current-Steering Digital-toAnalog Converters in 0.18-μm CMOS / IEEE Journal of Solid-State Circuits, 2007, vol.42, no. 8, pp. 1688–1698.1474.12.A.
van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, W. Sansen. A 10-bit 1-GSample/sNyquist current-steering CMOS D/A converter / IEEE J. Solid-State Circuits, vol. 36, no.3, pp. 315–324, Mar. 2001.4.13.D. Mercer. A Study of Error Sources in Current Steering Digital-to-Analog Converters /2004 IEEE Custom Integrated Circuits Conference, May 2004.4.14.Свизев Григорий Альбертович. Методы снижения уровня статических идинамических искажений выходного сигнала быстродействующих КМОП ЦАП.Дисс. соиск. канд.
техн. н-к, ФГАОУ ВО «Южный федеральный университет», 2018.4.15.A. Razavi. Design of Analog CMOS Integrated Circuits. 2nd edition. McGraw-HillEducation, 2016.4.16.J. H. Kim; K. S. Yoon. An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with asymmetric two-stage current cell matrix architecture / IEEE Transactions on Circuits andSystems II: Analog and Digital Signal Processing, 1998, vol.
45, no. 12, pp. 1605–1609.4.17.S. Park, G. Kim, S.-C. Park, Wonchan Kim. A digital-to-analog converter based ondifferential-quad switching / IEEE Journal of Solid-State Circuits, 2002, vol. 37, no. 10,pp. 1335–1338.5.1.Y. Cong, R. L. Geiger. Switching sequence optimization for gradient error compensationin thermometer-decoded DAC arrays / IEEE Trans. Circuits Syst. II, Analog Digit.
SignalProcess, 2000, vol. 47, no. 7, pp. 585–595.5.2.D.-H. Lee, Y.-H. Lin, and T.-H. Kuo. Nyquist-Rate Current-Steering Digital-to-AnalogConverters With Random Multiple Data-Weighted Averaging Technique and QNRotated Walk Switching Scheme / IEEE Transactions on Circuits and Systems II: ExpressBriefs, 2006, vol.
53, no. 11, pp. 1264–1268.5.3.Z. Yu, D. Chen, R. Geiger. 1-D and 2-D switching strategies achieving near optimal INLfor thermometer-coded current steering DACs / Proceedings of the 2003 InternationalSymposium on Circuits and Systems (ISCAS), 2003, pp. 909–912.5.4.H. Chen, L. Liu, D. Li, Z. Chun, Z. Wang. A 12-bit current steering DAC with 2-dimensionalgradient-error tolerant switching scheme / Journal of Semiconductors, 2010, vol. 31,no.
10, pp. 105006-1–105006-6.1485.5.J. A. Starzyk, R. P. Mohn. Cost-Oriented Design of a 14-bit Current Steering DACMacrocell / Proceedings of the 2003 International Symposium on Circuits and Systems(ISCAS), 2003, vol. 1, pp. 965–968.5.6.R. K. Srivastava, A. Vellathu, S. V. R. Kaipu; H. S.
Jattana; A. Rampal. A Systematic methodto find an optimized quad-quadrant random walk sequence for reducing the mismatcheffect in current steering DAC / 2017 International conference on MicroelectronicDevices, Circuits and Systems (ICMDCS), 2017, pp. 1–6.5.7.A.
I. Konstantinov, M. S. Yenuchenko. Switching sequences for a systematic errorcompensation in unary DACs / IEEE Conference of Russian Young Researchers inElectrical and Electronic Engineering (EIConRus), 2017, pp. 309–313.5.8.Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, N. Yazawa. A 10-bit 70 MS/s CMOS D/Aconverter / IEEE J. Solid-State Circuits, 1991, vol. 26, pp. 637–642.5.9.B. Henriques, J. Franca. A high-speed programmable CMOS interface systemcombining D/A conversion and FIR filtering / IEEE J.
Solid-State Circuits, 1994, vol. 29,pp. 972–977.5.10.B. G. Henriques, K. Kananen, J. E. Franca, J. Rapeli. A 10 bit low-power CMOS D/Aconverter with on-chip gain error compensation / Proceedings of the IEEE 1995 CustomIntegrated Circuits Conference, 1995, pp. 215–2185.11.C. Lin, K. Bult. A 10-b, 500-Msamples/s CMOS in 0.6um / IEEE J. Solid-State Circuits,1998, vol. 33, pp. 1948–1958.5.12.H.-H. Bae, J.-S.
Yoon, M.-J. Lee, E.-S. Shin, S.-H. Lee. A 3 V 12b 100 MS/s CMOS D/Aconverter for high-speed system applications / Proceedings of the 2003 InternationalSymposium on Circuits and Systems, 2003, vol. 1, pp. I-869–I-872.5.13.M. Vadipour. Gradient error cancellation and quadratic Error Reduction in Unary andBinary D/A Converters / IEEE Transactions on Circuits and Systems II: Analog and DigitalSignal Processing, 2003, vol.
50, no. 12, pp. 1002–1007.5.14.C.-Y. Huang, T.-T. Hou, H.-Y. Wang. 12-bit 250-MHz Current-Steering DAC / 6thInternational Conference on ASIC, 2005, pp. 451- 454.5.15.P. Palmers, X. Wu, M. Steyaert. A 130 nm CMOS 6-bit Full Nyquist 3GS/s DAC / IEEEAsian Solid-State Circuits Conference, November 2007, pp. 348-351.1495.16.Z. Junlei, W. Yuan, Z. Zhihui, J. Song. A 14-bit 300MHz pipelined DEM DAC withenhanced dynamic linearity / 2010 Asia Pacific Conference on Postgraduate Researchin Microelectronics and Electronics (PrimeAsia), 2010, pp. 85-88.5.17.D.-H.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
