Руководство пользователя для Altera DE0-Nano (1131985), страница 8
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Click Next to skip in Add Files window. In the Family & Device Settings window, we willchoose device family and device settings appropriate for the DE0-Nano board. You should choosesettings the same, as shown in Figure 7-5. Then click Next to get to the window as shown inFigure 7-6.84Figure 7-5 New Project Wizard: Family & Device Settings [page 3 of 5]4. Click Next and will see a window as shown in Figure 7-7.
Figure 7-7 is a summary about thenew project. Click Finish to complete the New Project Wizard. Figure 7-8 show the new project.85Figure 7-6 New Project Wizard: EDA Tool Settings [page 4 of 5]Figure 7-7 New Project Wizard: Summary [page 5 of 5]86Figure 7-8 A New Complete Project5. Select Tools > SOPC Builder to open SOPC Builder, the Altera system generation tool, asshown in Figure 7-9.Figure 7-9 SOPC Builder Menu87Figure 7-10 Create New SOPC System [0]6. Rename System Name as shown in Figure 7-10 and Figure 7-11.
Click OK and your will see awindow as shown in Figure 7-12.Figure 7-11 Create New System [1]88Figure 7-12 Create New System[2]7. Click the clk_0 name in the Clock Settings table to rename clk_0 to clk_50. Press Enter tocomplete the update, as shown in Figure 7-13.Figure 7-13 Rename Clock Name8. In the left hand-side Component Library tree, select Library > Processors > Nios II Processorand click the Add… button to open the Nios II component wizard, as shown in Figure 7-14 andFigure 7-15.89Figure 7-14 Add NIOS II Processor90Figure 7-15 Nios II Processor9.
Click Finish to return to main window as shown in Figure 7-16.91Figure 7-16 Add Nios II CPU completely10. Select the cpu_0 component and right-click then select rename, after this, you can updatecpu_0 to cpu, as shown in Figure 7-17 and Figure 7-18.92Figure 7-17 Rename the CPU (1)Figure 7-18 Rename the CPU (2)9311. Add a second component by selecting Library > Interface Protocols > Serial > JTAG UARTand clicking the Add… button, as shown in Figure 7-19 and Figure 7-20.Figure 7-19 Add the JTAG UART component94Figure 7-20 JTAG UART’s add wizard12.
We are going to use the default settings for this component, so click Finish to close the wizardand return to the window as shown in Figure 7-21.95Figure 7-21 JTAG UART13. Select the jtag_uart_0 component and rename it to jtag_uart as shown in Figure 7-22.96Figure 7-22 Rename JTAG UART15. Add the Library > Memories and Memory Controllers > On-Chip > On-Chip Memory(RAM or ROM) component to system, as shown in Figure 7-23 and Figure 7-24.97Figure 7-23 Add On-Chip Memory98Figure 7-24 On-Chip Memory Box16. Modify Total memory size setting to 26000 as shown in Figure 7-25.
Click Finish to return tothe window as in Figure 7-26.99Figure 7-25 Update Total memory size100Figure 7-26 Add On-Chip memory17. Rename onchip_memory2_0 to onchip_memory2 as shown in Figure 7-27.Figure 7-27 Rename On-Chip memory18. Right click on the cpu component table and select Edit… from the list. Update the Reset Vectorand Exception Vector as shown in Figure 7-28. Then, click Finish to return to the window asshown Figure 7-29.101Figure 7-28 Update CPU settings102Figure 7-29 Updated CPU settings19. Add the Library > Peripherals > Microcontroller Peripherals >PIO (Parallel I/O)component to the system, as shown in Figure 7-30 and Figure 7-31.103Figure 7-30 Add PIO104Figure 7-31 Add PIO20.
Click Finish to use the default settings for this component. This closes the PIO wizard andreturns to the window shown in Figure 7-32.105Figure 7-32 PIO21. Rename pio_0 to pio_led as shown in Figure 7-33.Figure 7-33 Rename PIO10622. Select System > Auto-Assign Base Addresses as shown in Figure 7-34. Then, select File >Refresh System. After that you will find that there is no error in the message window as shown inFigure 7-35.Figure 7-34 Auto-Assign Base AddressesFigure 7-35 No errors or warnings10723. Click the Generate button, which will pop up a window, as shown in Figure 7-36. Click Save,which bring up the window in Figure 7-37.
Input the name, DE0_NANO_SOPC, and click thesave button. The compilation will automatically start. If there are no errors in the generation, thewindow will show a message of success, as shown in Figure 7-38.Figure 7-36 Generate SOPCFigure 7-37 Generate SOPC108Figure 7-38 SOPC Builder generation successful24. Click Exit to exit the SOPC Builder and return to the window as shown in Figure 7-39.Figure 7-39 Return to Quartus II after exiting SOPC Builder10925. Create a new Verilog HDL file, by selecting File > New, Verilog HDL File and click OK, asshown in Figure 7-40 and Figure 7-41.Figure 7-40 New Verilog fileFigure 7-41 New Verilog File11033.
Figure 7-42 show a blank Verilog file.Figure 7-42 A blank verilog file34. Type the following Verilog into the blank file, as shown in Figure 7-43. The moduleDE0_NANO_SOPC is the system created by SOPC Builder and its Verilog can be found in theDE0_NANO_SOPC.v file, as shown in111Figure 7-44 and Figure 7-45.module myfirst_niosii(CLOCK_50,LED);inputCLOCK_50;output [7:0]LED;DE0_NANO_SOPC DE0_NANO_SOPC_inst(.clk_50(CLOCK_50),.out_port_from_the_pio_led (LED),.reset_n(1'b1));endmodule112Figure 7-43 Input verilog TextFigure 7-44 Open DE0_NANO_SOPC.v113Figure 7-45 DE0_NANO_SOPC module35.
Save the newly created Verilog file as myfirst_niosii.v, as shown in Figure 7-46.Figure 7-46 Save the Verilog file11436. Compile the project, by selecting Processing > Start Compilation, as shown in Figure 7-47.Figure 7-48 shows the compilation process.Figure 7-47 Start CompilationFigure 7-48 Execute Compile11537. A dialog box will appear upon successful completion of the compile, as shown in Figure 7-49.Figure 7-49 Compile project completely38. Now, we will assign the inputs and outputs of the circuit to specific pins. Select Assignments >Pin Planner from the menubar, as shown in Figure 7-50.
The pin planner is shown in Figure 7-51.Figure 7-50 Pins menu116Figure 7-51 Blank Pins39. Input Location values as shown in Figure 7-52.Figure 7-52 Set Pins40. Close the pin planner and recompile the project.7.3 Download the Hardware DesignThis section describes how to download the configuration file to the board.Download the FPGA configuration file (i.e. the SRAM Object File (.sof) that contains the NIOS IIbased system) to the board by performing the following steps:1.
Connect the board to the host computer via the USB download cable.2. Start the NIOS II IDE.3. After the welcome page appears, click Workbench.4. Select Tools > Quartus II Programmer.5. Click Auto Detect. The device on your development board should be detected automatically.6. Click the top row to highlight it.1177. Click Change File.8. Browse to the myfirst_niosii project directory.9. Select the programming file (myfirst_niosii.sof).10. Click OK.11. Click Hardware Setup in the top, left comer of the Quartus II programmer window.
TheHardware Setup dialog box appears.12. Select USB-Blaster from the currently selected hardware drop-down list box, as shown inFigure 7-53.Note: If the appropriate download cable does not appear in the list, you must first install driversfor the cable. Refer to Quartus II Help for information on how to install the driver.Figure 7-53 Hardware Setup Window13. Click Close.14. Make sure the Program/Configure option for the programming file (see Figure 7-54 for anexample).15. Click Start.118Figure 7-54 Quartus II ProgrammerThe Progress meter sweeps to 100% after the configuration finished. When configuration iscomplete, the FPGA is configured with the Nios II system, but it does not yet have a C program inmemory to execute.The Nios II IDE build flow is an easy-to-use graphical user interface (GUI) that automates buildand makefile management.
The Nios II IDE integrates a text editor, debugger, the Nios II flashprogrammer, the Quartus II Programmer, and the Nios II C-to-Hardware (C2H) compiler GUI. Theincluded example software application templates make it easy for new software programmers to getstarted quickly. In this section you will use the Nios II IDE to compile a simple C language examplesoftware program to run on the Nios II system on your development board. You will create a newsoftware project, build it, and run it on the target hardware.
You will also edit the project, re-build it,and set up a debug session.1197.4 Create a hello_world Example ProjectIn this section you will create a new NIOS II C/C++ application project based on an installedexample. To begin, perform the following steps in the NIOS II IDE:1. Return to the NIOS II IDE.Note: you can close the Quartus II Programmer or leave it open in the background if you want toreload the processor system onto your development board quickly.2.
Select File > New > NIOS II C/C++ Application to open the New Project Wizard.3. In the New Project wizard, make sure the following things:a. Select the Hello World project template.b. Give the project a name. (hello_world_0 is default name)c. Select the target hardware system’s PTF file that is located in the previously created hardwareproject directory, as shown in Figure 7-55.120Figure 7-55 Nios II IDE New Project Wizard5.
Click Finish. The NIOS II IDE creates the hello_world_0 project and returns to the NIOS IIC/C++ project perspective, as shown in Figure 7-56.121Figure 7-56 Nios II IDE C++ Project Perspective for hello_world_0When you create a new project, the NIOS II IDE creates two new projects in the NIOS II C/C++Projects tab:■ hello_world_0 is your C/C++ application project. This project contains the source and headerfiles for your application.■ hello_world_0_syslib is a system library that encapsulates the details of the Nios II systemhardware.Note: When you build the system library for the first time the NIOS II IDE automatically generatesfiles useful for software development, including:● Installed IP device drivers, including SOPC component device drivers for the NIOS II hardwaresystem● Newlib C library: a richly featured C library for the NIOS II processor.● NIOS II software packages which includes NIOS II hardware abstraction layer, NichestackTCP/IP Network stack, NIOS II host file system, NIOS II read-only zip file system and Micrium’sµC/OS-II realtime operating system (RTOS).● system.h: a header file that encapsulates your hardware system.122● alt_sys_init.c: an initialization file that initializes the devices in the system.● Hello_world_0.elf: an executable and linked format file for the application located inhello_world_0 folder under the Debug directory.7.5 Build and Run the ProgramIn this section you will build and run the program.To build the program, right-click the hello_world_0 project in the Nios II C/C++ Projects tab andselect Build Project.
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