Руководство пользователя для Altera DE0-Nano (1131985), страница 5
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Users can copy the whole folder to a host computer without installingthe utility. Launch the DE0-Nano System Builder by executing the DE0_NANO_SystemBuilder.exeon the host computer and the GUI window will appear as shown in Figure 5-2.Figure 5-2The DE0-Nano System Builder windowInput Project NameInput project name as show in Figure 5-3.Project Name: Type in an appropriate name here, it will automatically be assigned as the name ofyour top-level design entity.36Figure 5-3The DE0-Nano Board Type and Project NameSystem ConfigurationUnder System Configuration users are given the flexibility of enabling their choice of includedcomponents on the DE0-Nano as shown in Figure 5-4.
Each component of the DE0-Nano is listedwhere users can enable or disable a component according to their design by simply marking a checkor removing the check in the field provided. If the component is enabled, the DE0-Nano SystemBuilder will automatically generate the associated pin assignments including the pin name, pinlocation, pin direction, and I/O standard.Figure 5-4System Configuration GroupGPIO Expansion37Users can connect GPIO expansion card onto GPIO header located on the DE0-Nano board asshown in Figure 5-5.
Select the appropriate daughter card you wish to include in your design fromthe drop-down menu. The system builder will automatically generate the associated pin assignmentsincluding the pin name, pin location, pin direction, and IO standard.If a customized daughter board is used, users can select “GPIO Default” followed by changing thepin name and pin direction according to the specification of the customized daughter board.Figure 5-5GPIO Expansion GroupThe “Prefix Name” is an optional feature which denotes the prefix pin name of the daughter cardassigned in your design.
Users may leave this field empty.Project Setting ManagementThe DE0-Nano System Builder also provides functions to restore default setting, loading a setting,and saving users’ board configuration file shown in Figure 5-6. Users can save the current boardconfiguration information into a .cfg file and load it to the DE0-Nano System Builder.38Figure 5-6Project SettingsProject GenerationWhen users press the Generate button, the DE0-Nano System Builder will generate thecorresponding Quartus II files and documents as listed in the Table 5-1:Table 5-1The files generated by DE0-Nano System BuilderNo.1Filename<Project name>.vDescriptionTop level Verilog HDL file for Quartus II2<Project name>.qpfQuartus II Project File3<Project name>.qsfQuartus II Setting File4<Project name>.sdcSynopsys Design Constraints file for Quartus II5<Project name>.htmPin Assignment DocumentUsers can use Quartus II software to add custom logic into the project and compile the project togenerate the SRAM Object File (.sof).39Chapter 6Tutorial: Creating an FPGA ProjectThis tutorial provides comprehensive information for understanding how to create a FPGA designand run it on the DE0-Nano development and education board.
The following sections provide aquick overview of the design flow, explaining what is needed to get started, and describe what istaught in this tutorial.6.1 Design FlowFigure 6-1shows a block diagram of the FPGA design flow.The first step in the FPGA design flow starts is design entry. The standard design entry methods areusing schematics or a hardware description language (HDL), such as Verilog HDL or VHDL. Thedesign entry step is where the designer creates the digital circuit to be implemented inside theFPGA.
The flow then proceeds through compilation, simulation, programming, and verification inthe FPGA hardware.Figure 6-1 Design FlowThis tutorial describes all of the steps except for simulation. Although it is not covered in thisdocument, simulation is very important to learn. There are two types of simulation, Functional andTiming Functional simulation allows you to verify that your hardware is performing the desiredfunctionality. Timing (or post place-and-route) simulation verifies that the design meets timing andfunctions appropriately in the device. Simulation tutorials can be found on the Altera UniversityProgram website at http://university.altera.com.406.2 Before You BeginThis tutorial assumes the following prerequisites■ You have a general understanding of FPGAs.
This tutorial does not explain the basic conceptsof programmable logic.■ You are somewhat familiar with digital circuit design and electronic design automation (EDA)tools.■ You have installed the Altera Quartus II 10.1 software on your computer. If you do not have theQuartus II software, you can download it from the Altera web site at www.altera.com/download.■ You have a DE0-Nano Development Board on which you will test your project. Using adevelopment board helps you to verify whether your design is really working.■ You have gone through the quick start guide and/or the getting started user guide for yourdevelopment kit. These documents ensure that you have:• Installed the required software.• Determined that the development board functions properly and is connected to your computer.Next step is to install the USB-Blaster driver, if not already done.
To install the driver, connect aUSB cable between the DE0-Nano board and a USB port on a computer that is running the QuartusII software.The computer will recognize the new hardware connected to its USB port, but it will be unable toproceed if it does not have the required driver already installed. If the USB-Blaster driver is notalready installed, the New Hardware Wizard in Figure 6-2 will appear.41Figure 6-2 Found New Hardware WizardThe desired driver is not available on the Windows Update Web site, therefore select “No, not thistime” and click Next. This leads to the window in Figure 6-3.Figure 6-3 The driver is found in a specific location42The driver is available within the Quartus II software.
Hence, select “Install from a list or specificlocation” and click Next to get to Figure 6-4.Figure 6-4 Specify the location of the driverNow, select “Search for the best driver in these locations” and click Browse to get to the pop-updialog box in Figure 6-5 Find the desired driver, which is at locationC:\altera\10.1\quartus\drivers\usb-blaster. Click OK and then upon returning to Figure 6-4 clickNext. At this point the installation will commence, but a dialog box in Figure 6-6 will appearindicating that the driver has not passed the Windows Logo testing. Click Continue Anyway.43Figure 6-5 Browse to find the locationFigure 6-6 There is no need to test the driver44The driver will now be installed as indicated in Figure 6-7. Click Finish and you can start using theDE0-Nano board.Figure 6-7 The driver is installed6.3 W hat You W ill Lear nIn this tutorial you will perform the following tasks:Create a design that causes LEDs on the development board to blink at two distinct rates.
Thisdesign is easy to create and gives you visual feedback that the design works. Of course, you can useyour DE0-Nano board to run other designs as well. For the LED design, you will write Verilog HDLcode for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock source,and add a 2-input multiplexer megafunction. When the design is running on the board, you canpress an input switch to multiplex the counter bits that drive the output LEDs.6.4 Assign T he DeviceBegin this tutorial by creating a new Quartus II project. A project is a set of files that maintaininformation about your FPGA design.
The Quartus II Settings File (.qsf) and Quartus II Project File(.qpf) files are the primary files in a Quartus II project. To compile a design or make pinassignments, you must first create a project. The steps used to create a project are:451. In the Quartus II software, select File > New Project Wizard. The Introduction page opens, asshown in Figure 6-8.Figure 6-8 New Project Wizard introduction2.Click Next.3. Enter the following information about your project: (Note: File names, project names, anddirectories in the Quartus II software cannot contain spaces.)a. What is the working directory for this project? Enter a directory in which you will store yourQuartus II project files for this design.
For example, E:\My_design\my_first_fpga.b.What is the name of this project? Type my_first_fpga.c. What is the name of the top-level design entity for this project? Type my_first_fpga. SeeFigure 6-9.46Figure 6-9 Project informationd.Click Next.e. In the next dialog box, you will assign a specific FPGA device to the design. Select theEP4CE22F17C6 device, as it is the FPGA on the DE0-Nano, as shown in Figure 6-10.47Figure 6-10 Specify the Device Examplef.Click Finish.4.
When prompted, select Yes to create the my_first_fpga project directory. You just created yourQuartus II FPGA project. Your project is now open in Quartus II, as shown in Figure 6-11.48Figure 6-11 my_first_fpga project6.5 Creating an FPGA designThis section describes how to create an FPGA design. This includes creating the top-level design,adding components (in Verilog HDL and using the megafunctions), adding pins and interconnectingall the components and pins.First, create a top-level module. In this tutorial, you will use schematic entry, via a Block DesignFile (.bdf).
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