Руководство пользователя для Altera DE0-Nano (1131985), страница 10
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Connect the trimmer to the ADCchannel which is selected by the DIP Switches (Analog_In0 ~ Analog_In7).133Figure 8-4 2X13 HeaderSystem RequirementsThe following items are required for the ADC Reading demonstration• DE0-Nano board x1• Trimmer Potentiometer x1• Wire Strip x3Hardware Setup• Figure 8-5 shows the hardware setup for the ADC Reading demonstration.134Figure 8-5 ADC Reading hardware setupNote: the setup shown above is connected ADC channel 1.Demonstration Source Code• Project directory: DE0_NANO_ADC• Bit stream used: DE0_NANO.sofDemonstration Batch FileDemo Batch File Folder: DE0_NANO_ADC\demo_batchThe demo batch file includes the following files:• FPGA Configure File: DE0_NANO.sof•Demonstration Setup• Make sure Quartus II is installed on your PC.• Connect the trimmer to corresponding ADC channel to read from, as well as the +3.3V andGND signals.• Adjust the DIP switch according to the ADC channel connected• Connect USB cable to the DE0-Nano board and install the USB Blaster driver if necessary.• Execute the demo batch file “DE0_NANO_ADC.bat” under the batch file folder,DE0_NANO_ADC\demo_batch.
This will load the demo into the FPGA.• Adjust the voltage using the trimmer and observe the measurements on the LEDs. Note a fullylit LED bar indicates the voltage is 3.3V and similarly no LED lit indicates 0V.1358.4 SOPC DemoThis demostration illustrates how to use the SOPC Builder to create a system with the followingfunctions:••••Control accelerometer through 3-wire SPI interfaceControl analog to digital conversion through 4-wire SPI interfaceAccess EEPROM memory through I2C interfaceAccess EPCS memorySystem Block DiagramThis section describes the SOPC System Block Diagram of this demo, as shown in Figure 8-6.Figure 8-6 SOPC Block DiagramA 50 MHz Clock is required for the SOPC System.
A NIOS II processor is included in the systemfor flow control. The PLL is used to generate clocks, including 100 MHz, 10 MHz and 2MHz. TheNIOS II Processor and SDRAM are running at 100 MHZ. The SDRAM is used to store the NIOS IIProgram.
The ADC SPI Controller is running at 2 MHz. The other peripheral controllers are runningat 10 MHz. The ADC SPI Controller and the Accelerometer SPI Controller are custom SOPCcomponent. The source code, for these two controllers, is located in the “ip” folder under thisQuartus II project. The other components are standard SOPC Builder components.136KEYThe KEY button is driven by PIO Controller with interrupt enabled. It is design to generate aninterrupt event when users click KEY0 or KEY1. The interrupt event is used to terminateaccelerometer and analog to digital conversion process in this demo.For default, the interrupt is disabled in the PIO Controller. Users can enable it with the parametersetting as shown in below Figure 8-7.Figure 8-7 PIO ControllerAccelerometer ControlThe accelerometer controller is a custom SOPC component developed by Terasic.
The source codeis available under the folder \DE0_NANO_SOPC_DEMO\ip\TARASIC_SPI_3WIRE.In this demo, the accelerometer is controlled through a 3-wire SPI. Before reading any data from theaccelerometer, master should set 1 on the SPI bit in the Register 0x31 – DATA_FORMAT register,as shown in below Figure 8-8, to set the device to 3-wire SPI mode.Figure 8-8 DATA_FORMAT Register137The data format is configured as 10 bits, right-justify, +/- 2g mode.
The output data rate isconfigured as 400 HZ. The X/Y/Z value is read using polling mode. Before reading X/Y/Z, themaster needs to make sure data is ready by reading the register 0x30-INT_SOURCE, as shownbelow Figure 8-9, and checking the DATA_READY bit. In the demo, multiple-byte read of sixbytes X/Y/Z, register from 0x32 to 0x37, is performed to prevent a change in data between reads ofsequential register. Note, the output data is twos complement with DATAx0 as the least significantbyte and DATAx1 as the most significant byte, where x represent X, Y, or Z.Figure 8-9 Register 0x30The SPI timing scheme follows clock polarity (CPOL)=1 and clock phase (CPHA)=1.
(CPOL)=1means the clock is high in idle. (CPHA)=1 means data is captured on clock’s rising edge and data ispropagated on a falling edge. The timing diagram of 3-wire SPI is shown below Figure 8-10:Figure 8-10 3-wire SPI Timing DiagramADC ControlThe Analog to Digital Conversion is controller through a 4-wire SPI interface with the timing dialoggiven below Figure 8-11. Note, the DIN signal is used to specify the channel (IN0~IN7) for thenext data conversion.
The DOUT signal is used to read the data conversion result whose channel isspecified in previous transaction. The first conversion result after power-up will be on IN0. Theoutput format of conversion result is straight binary.138Figure 8-11 4-wire SPI Timing DiagramEEPROM ControlEEPROM is accessed through the I2C interface.
In this demo, I2C signal is toggle by NIOS IIthrough the PIO controller. The I2C clock signal is driver by an OUTPUT PIO Controller and theI2C data signal is driver by a BIDIRECTION PIO Controller. The I2C C code is located in:DE0_NANO_SOPC_DEMO\software\DE0_NANO\terasic_lib\I2C.cEPCS ControlEPCS64 is accessed through the EPCS interface. In Quartus 10.0 or later, the EPCS pin assignmentis required and should be connected the pins to EPCS Controller as shown below Figure 8-12:Figure 8-12 EPCS interface connectionFor the EPCS access functions, users can refer to:DE0_NANO_SOPC_DEMO\software\DE0_NANO\terasic_lib\Flash.c139Demonstration Source Code• Project directory: DE0_NANO_SOPC_DEMO• Bit stream used: DE0_NANO.sof• NIOS II elf file: DE0_NANO.elfDemonstration Batch File• Demo Batch File Folder: DE0_NANO_SOPC_DEMO\demo_batchThe demo batch file includes the file:• Batch File: test.bat and test_bashrc• FPGA Configure File: DE0_NANO.sof• Nios II Program: DE0_NANO.elfDemonstration Setup• Make sure Quartus II and Nios II are installed on your PC.• Connect a USB cable to the DE0-Nano board and install USB Blaster driver if necessary.• Execute the demo batch file “test.bat” under the batch file folder,DE0_NANO_SOPC_DEMO\demo_batch.
This will load the demo into the FPGA.• After executing the batch file, a selection menu appears as follows:• Input “0” to start the accelerometer demo. The demo starts by displaying the accelerometer’schip ID, and then continues by displaying the X/Y/Z values every 1.0 second. Toterminate the demo, press KEY0 or KEY1 on the DE0-Nano board. Upon exiting thedemo, the selection menu will be displayed.140• Input “1” to start Analog to Digital Conversion demo. The demo repeatedly displays thevoltage on eight channels. To terminate the process, press KEY0 or KEY1 on theDE0-Nano board. Upon exiting the demo, the selection menu will be displayed.• Input “2” to start EEPROM Content Dump demo.
The demo displays the values in the first 16bytes of the EEPROM. The demo automatically exists, and returns to the selection menu.• Input “3” to start EPCS demo. The demo displays the memory size of EPCS. The demoautomatically exists, and returns to the selection menu.1418.5 G-SensorThis demonstration illustrates how to use the digital accelerometer on the DE0-Nano board to measurethe static acceleration of gravity in tilt-sensing applications. As the board is tilted from left to right andright to left, the digital accelerometer detects the tilting movement and displays it on the LEDs.Figure 8-13 DE0-Nano on level surfaceDesign ConceptThis section describes the design concepts for this demo.
Figure 8-14 shows the block diagram.Figure 8-14 G-Sensor block diagram142In this demo, the accelerometer is controlled through a 3-wire SPI. Before reading any data from theaccelerometer, the controller sets 1 on the SPI bit in the Register 0x31 – DATA_FORMAT register.The 3-wire SPI Controller block reads the digital accelerometer X-axis value, to determine the tiltof the board. The LEDs are lit up as if they were a bubble, floating to the top of the board.Demonstration Source Code• Project directory: DE0_NANO_GSensor• Bit stream used: DE0_NANO_G_Sensor.sofDemonstration Batch FileDemo Batch File Folder: DE0_NANO_GSensor\demo_batchThe demo batch file includes the following files:• FPGA Configure File: DE0_NANO_G_Sensor.sofDemonstration Setup• Make sure Quartus II is installed on your PC.• Connect USB cable to the DE0-Nano board and install the USB Blaster driver if necessary.• Execute the demo batch file “test.bat” under the batch file folder,DE0_NANO_GSensor\demo_batch.
This will load the demo into the FPGA.• Tilt the DE0-Nano board from side to side and observe the result on the LEDs.8.6 SDRAM Test by Nios IIMany applications use SDRAM to provide temporary storage. In this demonstration hardware andsoftware designs are provided to illustrate how to perform memory access in QSYS. We describehow the Altera’s SDRAM Controller IP is used to access a SDRAM, and how the Nios II processoris used to read and write the SDRAM for hardware verification. The SDRAM controller handles thecomplex aspects of using SDRAM by initializing the memory devices, managing SDRAM banks,and keeping the devices refreshed at appropriate intervals.System Block DiagramFigure 8-15 shows the system block diagram of this demonstration. The system requires a 50 MHzclock provided from the board.
The SDRAM controller is configured as a 32MB controller. Theworking frequency of the SDRAM controller is 100MHz, and the Nios II program is running in theSDRAM.143Figure 8-15 Block diagram of the SDRAM Basic DemonstrationThe system flow is controlled by a Nios II program. First, the Nios II program writes test patternsinto the SDRAM.
Then, it calls Nios II system function, alt_dcache_flush_all, to make sure all datahas been written to SDRAM. Finally, it reads data from SDRAM for data verification. The programwill show progress in JTAG-Terminal when writing/reading data to/from the SDRAM. Whenverification process is completed, the result is displayed in the JTAG-Terminal.Design Tools••Quartus II 13.0 SP1Nios II Eclipse 13.0 SP1Demonstration Source Code••Quartus Project directory: DE0_NANO_SDRAM_Nios_TestNios II Eclipse: DE0_NANO_SDRAM_Nios_Test \SoftwareNios II Project Compilation•Before you attempt to compile the reference design under Nios II Eclipse, make sure the projectis cleaned first by clicking ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.144Demonstration Batch FileDemo Batch File Folder: DE0_NANO_SDRAM_Nios_Test \demo_batchThe demo batch file includes following files:•••Batch File for USB-Blaster : DE0_NANO_SDRAM_Nios_Test.bat,DE0_NANO_SDRAM_Nios_Test.shFPGA Configure File : DE0_NANO_SDRAM_Nios_Test.sofNios II Program: DE0_NANO_SDRAM_Nios_Test.elfDemonstration Setup•••••Make sure Quartus II and Nios II are installed on your PC.Connect a USB cable to the DE0-Nano board and install USB Blaster driver if necessary.Execute the demo batch file “ DE0_NANO_SDRAM_Nios_Test .bat” under the batch filefolder, DE0_NANO_SDRAM_Nios_Test \demo_batchAfter Nios II program is downloaded and executed successfully, a prompt message will bedisplayed in nios2-terminal.Press KEY1~KEY0 of the DE0-Nano board to start SDRAM verify process.
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