Руководство пользователя для Altera DE0-Nano (1131985), страница 3
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The chip uses 3.3V LVCMOS signalingstandard. All signals are registered on the positive edge of the clock signal, DRAM_CLK.Connections between the FPGA and SDRAM chips are shown in Figure 3-6.Figure 3-6Connections between FPGA and SDRAMTable 3-4 SDRAM Pin AssignmentsSignal NameDRAM_ADDR[0]DRAM_ADDR[1]DRAM_ADDR[2]DRAM_ADDR[3]DRAM_ADDR[4]DRAM_ADDR[5]DRAM_ADDR[6]DRAM_ADDR[7]DRAM_ADDR[8]DRAM_ADDR[9]DRAM_ADDR[10]DRAM_ADDR[11]FPGA Pin No.PIN_P2PIN_N5PIN_N6PIN_M8PIN_P8PIN_T7PIN_N8PIN_T6PIN_R1PIN_P1PIN_N2PIN_N1DescriptionSDRAM Address[0]SDRAM Address[1]SDRAM Address[2]SDRAM Address[3]SDRAM Address[4]SDRAM Address[5]SDRAM Address[6]SDRAM Address[7]SDRAM Address[8]SDRAM Address[9]SDRAM Address[10]SDRAM Address[11]15I/O Standard3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3VDRAM_ADDR[12]DRAM_DQ[0]DRAM_DQ[1]DRAM_DQ[2]DRAM_DQ[3]DRAM_DQ[4]DRAM_DQ[5]DRAM_DQ[6]DRAM_DQ[7]DRAM_DQ[8]DRAM_DQ[9]DRAM_DQ[10]DRAM_DQ[11]DRAM_DQ[12]DRAM_DQ[13]DRAM_DQ[14]DRAM_DQ[15]DRAM_BA[0]DRAM_BA[1]DRAM_DQM[0]DRAM_DQM[1]DRAM_RAS_NDRAM_CAS_NDRAM_CKEDRAM_CLKDRAM_WE_NDRAM_CS_NPIN_L4PIN_G2PIN_G1PIN_L8PIN_K5PIN_K2PIN_J2PIN_J1PIN_R7PIN_T4PIN_T2PIN_T3PIN_R3PIN_R5PIN_P3PIN_N3PIN_K1PIN_M7PIN_M6PIN_R6PIN_T5PIN_L2PIN_L1PIN_L7PIN_R4PIN_C2PIN_P6SDRAM Address[12]SDRAM Data[0]SDRAM Data[1]SDRAM Data[2]SDRAM Data[3]SDRAM Data[4]SDRAM Data[5]SDRAM Data[6]SDRAM Data[7]SDRAM Data[8]SDRAM Data[9]SDRAM Data[10]SDRAM Data[11]SDRAM Data[12]SDRAM Data[13]SDRAM Data[14]SDRAM Data[15]SDRAM Bank Address[0]SDRAM Bank Address[1]SDRAM byte Data Mask[0]SDRAM byte Data Mask[1]SDRAM Row Address StrobeSDRAM Column Address StrobeSDRAM Clock EnableSDRAM ClockSDRAM Write EnableSDRAM Chip Select3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.4 I2C Serial EEPROMThe DE0-Nano contains a 2Kbit Electrically Erasable PROM (EEPROM).
The EEPROM isconfigured through a 2-wire I2C serial interface. The device is organized as one block of 256 x 8-bitmemory. The I2C write and read address are 0xA0 and 0xA1, respectively. Figure 3-7 illustrates itsconnections with the Cyclone IV FPGA.16Figure 3-7Connections between FPGA and EEPROMTable 3-5 Pin Assignments for I2C Serial EEPROMSignal NameI2C_SCLKI2C_SDATFPGA Pin No.PIN_F2PIN_F1DescriptionEEPROM clockEEPROM dataI/O Standard3.3V3.3V3.5 Expansion HeadersThe DE0-Nano board provides two 40-pin expansion headers.
Each header connects directly to 36pins of the Cyclone IV E FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and twoGND pins. Figure 3-8 shows the I/O distribution of the GPIO connectors.17Figure 3-8Pin arrangement of the GPIO expansion headersThe pictures below indicate the pin 1 location of the expansion headers.Figure 3-9Pin1 locations of the GPIO expansion headersTable 3-6 GPIO-0 Pin AssignmentsSignal NameFPGA Pin No.DescriptionGPIO_0_IN0PIN_A8GPIO Connection DATAI/O Standard3.3VGPIO_00PIN_D3GPIO Connection DATA3.3VGPIO_0_IN1PIN_B8GPIO Connection DATA3.3VGPIO_01PIN_C3GPIO Connection DATA3.3V18GPIO_02PIN_A2GPIO Connection DATA3.3VGPIO_03PIN_A3GPIO Connection DATA3.3VGPIO_04PIN_B3GPIO Connection DATA3.3VGPIO_05PIN_B4GPIO Connection DATA3.3VGPIO_06PIN_A4GPIO Connection DATA3.3VGPIO_07PIN_B5GPIO Connection DATA3.3VGPIO_08PIN_A5GPIO Connection DATA3.3VGPIO_09PIN_D5GPIO Connection DATA3.3VGPIO_010PIN_B6GPIO Connection DATA3.3VGPIO_011PIN_A6GPIO Connection DATA3.3VGPIO_012PIN_B7GPIO Connection DATA3.3VGPIO_013PIN_D6GPIO Connection DATA3.3VGPIO_014PIN_A7GPIO Connection DATA3.3VGPIO_015PIN_C6GPIO Connection DATA3.3VGPIO_016PIN_C8GPIO Connection DATA3.3VGPIO_017PIN_E6GPIO Connection DATA3.3VGPIO_018PIN_E7GPIO Connection DATA3.3VGPIO_019PIN_D8GPIO Connection DATA3.3VGPIO_020PIN_E8GPIO Connection DATA3.3VGPIO_021PIN_F8GPIO Connection DATA3.3VGPIO_022PIN_F9GPIO Connection DATA3.3VGPIO_023PIN_E9GPIO Connection DATA3.3VGPIO_024PIN_C9GPIO Connection DATA3.3VGPIO_025PIN_D9GPIO Connection DATA3.3VGPIO_026PIN_E11GPIO Connection DATA3.3VGPIO_027PIN_E10GPIO Connection DATA3.3VGPIO_028PIN_C11GPIO Connection DATA3.3VGPIO_029PIN_B11GPIO Connection DATA3.3VGPIO_030PIN_A12GPIO Connection DATA3.3VGPIO_031PIN_D11GPIO Connection DATA3.3VGPIO_032PIN_D12GPIO Connection DATA3.3VGPIO_033PIN_B12GPIO Connection DATA3.3VTable 3-7 GPIO-1 Pin AssignmentsSignal NameFPGA Pin No.DescriptionGPIO_1_IN0PIN_T9GPIO Connection DATAI/O Standard3.3VGPIO_10PIN_F13GPIO Connection DATA3.3VGPIO_1_IN1PIN_R9GPIO Connection DATA3.3VGPIO_11PIN_T15GPIO Connection DATA3.3VGPIO_12PIN_T14GPIO Connection DATA3.3VGPIO_13PIN_T13GPIO Connection DATA3.3VGPIO_14PIN_R13GPIO Connection DATA3.3VGPIO_15PIN_T12GPIO Connection DATA3.3V19GPIO_16PIN_R12GPIO Connection DATA3.3VGPIO_17PIN_T11GPIO Connection DATA3.3VGPIO_18PIN_T10GPIO Connection DATA3.3VGPIO_19PIN_R11GPIO Connection DATA3.3VGPIO_110PIN_P11GPIO Connection DATA3.3VGPIO_111PIN_R10GPIO Connection DATA3.3VGPIO_112PIN_N12GPIO Connection DATA3.3VGPIO_113PIN_P9GPIO Connection DATA3.3VGPIO_114PIN_N9GPIO Connection DATA3.3VGPIO_115PIN_N11GPIO Connection DATA3.3VGPIO_116PIN_L16GPIO Connection DATA3.3VGPIO_117PIN_K16GPIO Connection DATA3.3VGPIO_118PIN_R16GPIO Connection DATA3.3VGPIO_119PIN_L15GPIO Connection DATA3.3VGPIO_120PIN_P15GPIO Connection DATA3.3VGPIO_121PIN_P16GPIO Connection DATA3.3VGPIO_122PIN_R14GPIO Connection DATA3.3VGPIO_123PIN_N16GPIO Connection DATA3.3VGPIO_124PIN_N15GPIO Connection DATA3.3VGPIO_125PIN_P14GPIO Connection DATA3.3VGPIO_126PIN_L14GPIO Connection DATA3.3VGPIO_127PIN_N14GPIO Connection DATA3.3VGPIO_128PIN_M10GPIO Connection DATA3.3VGPIO_129PIN_L13GPIO Connection DATA3.3VGPIO_130PIN_J16GPIO Connection DATA3.3VGPIO_131PIN_K15GPIO Connection DATA3.3VGPIO_132PIN_J13GPIO Connection DATA3.3VGPIO_133PIN_J14GPIO Connection DATA3.3V3.6 A/D Conver ter and 2x13 HeaderThe DE0-Nano contains an ADC128S022 lower power, eight-channel CMOS 12-bitanalog-to-digital converter.
This A-to-D provides conversion throughput rates of 50 ksps to 200ksps. It can be configured to accept up to eight input signals at inputs IN0 through IN7. This eightinput signals are connected to the 2x13 header, as shown in Figure 3-10. The remaining I/Os of the2x13 header are a DC +3.3V (VCC33), a GND and 13 pins, which are connect directly to theCyclone IV E device.For more detailed information on the A/D converter chip, please refer to its datasheet which isavailable on manufacturer’s website or under the /datasheet folder of the system CD.20Figure 3-10Pin distribution of the 2x13 HeaderFigure 3-11 shows the connections on the 2x13 header, A/D converter and Cyclone IV device.Figure 3-11Wiring for 2x13 header and A/D converterThe pictures below indicate the pin 1 location of the 2x13 header.21Figure 3-12Pin1 locations of the 2x13 headerTable 3-8 Pin Assignments for 2x13 HeaderSignal NameGPIO_2[0]GPIO_2[1]GPIO_2[2]GPIO_2[3]GPIO_2[4]GPIO_2[5]GPIO_2[6]GPIO_2[7]GPIO_2[8]GPIO_2[9]GPIO_2[10]GPIO_2[11]GPIO_2[12]GPIO_2_IN[0]GPIO_2_IN[1]FPGA Pin No.PIN_A14PIN_B16PIN_C14PIN_C16PIN_C15PIN_D16PIN_D15PIN_D14PIN_F15PIN_F16PIN_F14PIN_G16PIN_G15PIN_E15PIN_E16DescriptionGPIO Connection DATA[0]GPIO Connection DATA[1]GPIO Connection DATA[2]GPIO Connection DATA[3]GPIO Connection DATA[4]GPIO Connection DATA[5]GPIO Connection DATA[6]GPIO Connection DATA[7]GPIO Connection DATA[8]GPIO Connection DATA[9]GPIO Connection DATA[10]GPIO Connection DATA[11]GPIO Connection DATA[12]GPIO InputGPIO InputI/O Standard3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3VGPIO_2_IN[2]PIN_M16GPIO Input3.3VTable 3-9 Pin Assignments for ADCSignal NameADC_CS_NADC_SADDRADC_SDATADC_SCLKFPGA Pin No.PIN_A10PIN_B10PIN_A9PIN_B14DescriptionChip selectDigital data inputDigital data outputDigital clock input22I/O Standard3.3V3.3V3.3V3.3V3.7 Digital AccelerometerThe ADXL345 is a small, thin, ultralow power, 3-axis accelerometer with high resolutionmeasurement.
This digital accelerometer can be accessed through a SPI 3-wire digital interface orI2C 2-wire digital interface. Main applications include medical instrumentation, industrialinstrumentation, personal electronic aid and hard disk drive protection etc. Some of the key featuresof this device are listed below. For more detailed information, please refer to its datasheet which isavailable on manufacturer’s website or under the /datasheet folder of the system CD.•••Up to 13-bit resolution at +/- 16gSPI (3- wire) or I2C (2-wire) digital interfaceFlexible interrupts modesFigure 3-13 shows the connections between the ADXL345 and the Cyclone IV E device.Figure 3-13Wiring between the ADXL345 and the Cyclone IV E deviceTable 3-10 Pin Assignments for Digital AccelerometerSignal NameI2C_SCLKI2C_SDATG_SENSOR_INTG_SENSOR_CS_NFPGA Pin No.PIN_F2PIN_F1PIN_M2PIN_G5DescriptionEEPROM clockEEPROM dataG_Sensor InterruptG_Sensor chip selectI/O Standard3.3V3.3V3.3V3.3V3.8 Clock Circuitr yThe DE0-Nano board includes a 50 MHz oscillator.
The oscillator is connected directly to adedicated clock input pin of the Cyclone IV E FPGA. The 50MHz clock input can be used as asource clock to drive the phase lock loops (PLL) circuit. The clock distribution on the DE0-Nanoboard is shown in Figure 3-14.23Figure 3-14Block diagram of the clock distribution3.9 Power SupplyThe DE0-Nano board’s power is provided through the USB 5V power, the 5V VCC pins on the two40-pin headers or the 2-pin power header. The DC voltage is then stepped down to various requiredvoltages. For portable project applications, connect a battery power supply (3.6~5.7V) to the 2-pinexternal power header shown in Figure 3-15.Figure 3-15Portable Battery Connection24Power Distribution SystemFigure 3-16 shows the power distribution system on the DE0-Nano board.Figure 3-16DE0-Nano Power Distribution System25Chapter 4DE0DE0-Nano Control PanelThe DE0-Nano board comes with a Control Panel facility that allows users to access variouscomponents on the board from a host computer.
The host computer communicates with the boardthrough a USB connection. The facility can be used to verify the functionality of components on theboard or be used as a debug tool while developing RTL code.This chapter first presents some basic functions of the Control Panel, then describes its structure inblock diagram form, and finally describes its capabilities.4.1 Control Panel SetupThe Control Panel Software Utility is located in the directory “tools/DE0_NANO_ControlPanel” inthe DE0-Nano System CD.
It's free of installation, just copy the whole folder to your host computerand launch the control panel by executing the “DE0_NANO_ControlPanel.exe”.When Control Panel starts it will attempt to download a configuration file onto the DE0-Nano board.The configuration file contains a design that communicates with the peripheral devices on the boardthat are attached to the FPGA device. Perform the following steps to ensure that the control panelstarts up successfully:1.Make sure Quartus II 10.0 or later version is installed successfully on your PC.2.Connect a USB A to Mini-B cable to a USB (Type A) host port and to the board.3.
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