Руководство пользователя для Altera DE0-Nano (Лабораторная работа 2), страница 7

Name the bus counter [24..21], which selects only those counter output bits to connect to thefour bits of the data1x input.h.Click OK. Figure 6-37 shows the renamed buses.Figure 6-37 Renamed counter_bus_mux Bus LinesIf you have not done so already, you may want to save your project file before continuing.16. Right click in the blank area of the BDF and select Insert > Symbol.17. Under Libraries, select quartus/libraries > primitives > pin >output, as shown in Figure 6-38.69Figure 6-38 Choose output pin18.

Click OK.19. Place this output pin so that it connects to the counter_bus_mux’s result [3..0] bus output line.20. Rename the output pin as LED [3..0]. (see Figure 6-39).Figure 6-39 Rename the output pin21. Attach an input pin to the multiplexer select line using an input pin:a.Right click in the blank area of the BDF and select Insert > Symbol.b.Under Libraries, double-click quartus/libraries/ > primitives > pin > input.c.Click OK.22.

Place this input pin below counter_bus_mux.23. Connect the input pin to the counter_bus_mux sel pin.24. Rename the input pin as KEY [0] (see Figure 6-40).70Figure 6-40 Adding the KEY [0] Input PinYou have finished adding all required components of the circuit to your design. You can add notesor information to the project as text using the Text tool on the toolbar (indicated with the A symbol).For example, you can add the label “OFF = SLOW, ON = FAST” to the KEY [0] input pin and adda project description, such as “DE0-Nano Tutorial Project.”6.6 Assign the PinsIn this section, you will make pin assignments. Before making pin assignments, perform thefollowing steps:1. Select Processing > Start > Start Analysis & Elaboration in preparation for assigning pinlocations.2.Click OK in the message window that appears after analysis and elaboration completes.To make pin assignments to the KEY [0] and CLOCK_50 input pins and to the LED[3..0] outputpins, perform the following steps:1.

Select Assignments > Pin Planner, which opens the Pin Planner, a spreadsheet-like table ofspecific pin assignments. The Pin Planner shows the design’s six pins. See Figure 6-4171Figure 6-41 Pin Planner Example2. In the Location column next to each of the six node names, add the coordinates (pin numbers)as shown in Table 6-1 for the actual values to use with your DE0-Nano board.Table 6-1 Pin Information SettingPin NameKEY[0]LED[3]LED[2]LED [1]LED [0]CLOCK_50FPGA Pin LocationJ15A11B13A13A15R8Double-click in the Location column for any of the six pins to open a drop-down list and type thelocation shown in the table. Alternatively, you can select the pin from a drop-down list. For example,if you type F1 and press the Enter key, the Quartus II software fills in the full PIN_F1 locationname for you. The software also keeps track of corresponding FPGA data such as the I/O bank andVREF Group.

Each bank has a distinct color, which corresponds to the top-view wire bond drawingin the upper right window, as shown in Figure 6-42.72Figure 6-42 Completed Pin Planning ExampleNow, you are finished creating your Quartus II design!6.7 Create a Default TimeQuest SDC FileTiming settings are critically important for a successful design.

For this tutorial you will create abasic Synopsys Design Constraints File (.sdc) that the Quartus II TimeQuest Timing Analyzer usesduring design compilation. For more complex designs, you will need to consider the timingrequirements more carefully.To create an SDC, perform the following steps:1.Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer.2.Select File > New SDC file. The SDC editor opens.3.Type the following code into the editor:create_clock -period 20.000 -name CLOCK_50derive_pll_clocksderive_clock_uncertainty4.Save this file as my_first_fpga.sdc (see Figure 6-43)73Figure 6-43 Default SDCNaming the SDC with the same name as the top-level file causes the Quartus II software to use thistiming analysis file automatically by default. If you used another name, you would need to add theSDC to the Quartus II assignments file.6.8 Compile Your DesignAfter creating your design you must compile it.

Compilation converts the design into a bitstreamthat can be downloaded into the FPGA. The most important output of compilation is an SRAMObject File (.sof), which you use to program the device. Also, the software generates report filesthat provide information about your circuit as it compiles.Now that you have created a complete Quartus II project and entered all assignments, you cancompile the design.In the Processing menu, select Start Compilation or click the Play button on the toolbar.If you are asked to save changes to your BDF, click Yes.While compiling your design, the Quartus II software provides useful information about thecompilation, as shown in Figure 6-44.74Figure 6-44 Compilation Message for projectWhen compilation is complete, the Quartus II software displays a message. Click OK to close themessage box.The Quartus II Messages window displays many messages during compilation.

It should not displayany critical warnings; it may display a few warnings that indicate that the device timing informationis preliminary or that some parameters on the I/O pins used for the LEDs were not set. The softwareprovides the compilation results in the Compilation Report tab as shown in Figure 6-45.75Figure 6-45 Compilation Report Example6.9 Program the FPGA DeviceAfter compiling and verifying your design you are ready to program the FPGA on the developmentboard.

You download the SOF you just created into the FPGA using the USB-Blaster circuitry onthe board. Set up your hardware for programming using the following steps:First, connect the USB cable, which was included in your development kit, between the DE0-Nanoand the host computer. Refer to the getting started user guide for detailed instructions on how toconnect the cables.Refer to the getting started user guide for detailed instructions on how to connect the cables.Program the FPGA using the following steps.1.Select Tools > Programmer. The Programmer window opens, as shown in Figure 6-46.76Figure 6-46 Programmer Window2.Click Hardware Setup.3. If it is not already turned on, turn on the USB-Blaster [USB-0] option under currently selectedhardware, as shown in Figure 6-47.77Figure 6-47 Hardware Setting4.Click Close.5.If the file name in the Programmer does not show my_first_fpga.sof, click Add File.6.Select the my_first_fpga.sof file from the project directory (see Figure 6-48).7.Click the Start button.78Figure 6-48 Downloading CompleteCongratulations, you have created, compiled, and programmed your first FPGA design! Thecompiled SRAM Object File (.sof) is loaded onto the FPGA on the development board and thedesign should be running.6.10 Verify T he HardwareWhen you verify the design in hardware, you observe the runtime behavior of the FPGA hardwaredesign and ensure that it is functioning appropriately.Verify the design by performing the following steps:1.

Observe that the four development board LEDs appear to be advancing slowly in a binary countpattern, which is driven by the simple_counter bits [26..23].The LEDs are active low, therefore, when counting begins all LEDs are turned on (the 0000 state).2. Press and hold KEY [0] on the development board and observe that the LEDs advance morequickly.

Pressing this KEY causes the design to multiplex using the faster advancing part of thecounter (bits [24..21]).3. If other LEDs emit faintness light, select Assignments > Device. Click Device and Options. SeeFigure 6-49.79Figure 6-49 Device and OptionsSelect unused pins. Reserve all unused pins: select the As input tri-stated option. See Figure 6-50.80Figure 6-50 Setting unused pinsClick twice OK.4. In the Processing menu, choose Start Compilation. After the compile, select Tools >Programmer. Select the my_first_fpga.sof file from the project directory.

Click Start. At this timeyou could find the other LEDs are off.81Chapter 7Tutorial: Creating a Nios II ProjectThis tutorial provides comprehensive information that will help you understand how to create amicroprocessor system on your FPGA development board and run software on it. This system willbe based on the Altera Nios II processor.7.1 Required FeaturesThis tutorial requires the Quartus II and Nios II EDS software to be installed. The tutorial waswritten for version 10.1 of those software packages.

If you are using a different version, there maybe some difference in the flow. Also, this tutorial requires the DE0-Nano board.7.2 Creation of Hardware DesignThis section describes the flow of how to create a hardware system including a Nios II processor.1. Launch Quartus II then select File > New Project Wizard, start to create a new project. SeeFigure 7-1and Figure 7-2.82Figure 7-1 Start to Create a New ProjectFigure 7-2 New Project Wizard2. Select a working directory for this project, type project name and top-level entity name as shownin Figure 7-3. Then click Next, you will see a window as shown in Figure 7-4.83Figure 7-3 Input the working directory, the name of project, top-level design entityFigure 7-4 New Project Wizard: Add Files [page 2 of 5]3.