Руководство пользователя для Altera DE0-Nano (Лабораторная работа 2), страница 6

Alternatively, you could use Verilog HDL or VHDL for the top-level module. Thefollowing steps describe how to create the top-level schematic.1. Select File > New > Block Diagram/Schematic File (see Figure 6-12 to create a new file,Block1.bdf, which you will save as the top-level design.49Figure 6-12 New BDF2.Click OK.3.Select File > Save As and enter the following information.• File name: my_first_fpga• Save as type: Block Diagram/Schematic File (*.bdf)4.Click Save. The new design file appears in the Block Editor (see Figure 6-13).50Figure 6-13 Bank BDFAdding a Verilog HDL to the Schematic1.Add HDL code to the blank block diagram by choosing File > New > Verilog HDL File.2.Select Verilog HDL File in the tree and Click OK.3.

Save the newly created file, by selecting File > Save As and entering the following information(see Figure 6-14).• File name: simple_counter.v• Save as type: Verilog HDL File (*.v, *.vlg, *.verilog)51Figure 6-14 Saving the Verilog HDL fileThe resulting empty file is ready for you to enter the Verilog HDL code.4. Type the following Verilog HDL code into the blank simple_counter.v file, as shown in Figure6-15.//It has a single clock input and a 32-bit output portmodule simple_counter (CLOCK_5,counter_out);inputCLOCK_5 ;output [31:0] counter_out;reg[31:0] counter_out;52always @ (posedge CLOCK_5)// on positive clock edgebegincounter_out <= counter_out + 1;// increment counterendendmodule// end of module counterFigure 6-15 The Verilog File of simple_counter.v5.Save the file by choosing File > Save, pressing Ctrl + S, or by clicking the floppy disk icon.6.

Select File > Create/Update > Create Symbol Files for Current File to convert thesimple_counter.v file to a Symbol File (.sym). You will use this Symbol File to add the HDL codeto your schematic.The Quartus II software creates a Symbol File and displays a message (see Figure 6-16).Figure 6-16 Create Symbol File was Successful7.Click OK.8.To add the simple_counter.v symbol to the top-level design, click the my_first_fpga.bdf tab.539.Right click in the blank area of the BDF file, and select Insert > Symbol.10. Double-click the Project directory to expand it.11.

Select the newly created simple_counter symbol by clicking its icon.Figure 6-17 Adding the Symbol to the BDF12.Click OK.13. Move the cursor to the BDF grid; the symbol image moves with the cursor. Click to place thesimple_counter symbol onto the BDF. You can move the block after placing it by simply clickingand dragging it to where you want it and releasing the mouse button to place it. See Figure 6-18.Figure 6-18 Placing the simple_counter symbol5414.Press the Esc key or click an empty place on the schematic grid to cancel placing furtherinstances of this symbol.15.Save your project regularly.Adding a Megafunction to the SchematicMegafunctions, such as the ones available in the LPM, are pre-designed modules that you can use inFPGA designs.

These Altera-provided megafunctions are optimized for speed, area, and devicefamily. You can increase efficiency by using a megafunction instead of writing the function yourself.Altera also provides more complex functions, called MegaCore functions, which you can evaluatefor free but require a license file for use in production designs. This tutorial design uses a PLL clocksource to drive a simple counter. A PLL uses the on-board oscillator (DE0-Nano Board is 50 MHz)to create a constant clock frequency as the input to the counter. To create the clock source, you willadd a pre-built LPM megafunction named ALTPLL.1.

Right click in the blank space in the BDF and select Insert > Symbol or click the Add Symbolicon on the toolbar.2. Click the Megawizard Plug-in Manager button. The MegaWizard® Plug-In Manager appears,as shown in Figure 6-19.Figure 6-19 Mega Wizard Plug-In Manager553.Click Next.4.In MegaWizard Plug-In Manager [page 2a], specify the following selections (see Figure 6-20):a.Select I/O > ALTPLL.b. Under “Which device family will you be using?” select the Cyclone IV E for DE0-Nanodevelopment board.c.Under “Which type of output file do you want to create?” select Verilog HDL.d.

Under “What name do you want for the output file?” type pll at the end of the already createddirectory name.e.Click Next.Figure 6-20 MegaWizard Plug-In Manager [page 2a] Selections5. In the MegaWizard Plug-In Manager [page 3 of 14] window, make the following selections(see Figure 6-21).a.Confirm that the currently selected device family option is set to Cyclone IV E.b.For device speed grade choose 6 for DE0-Nano.c.Set the frequency of the inclock0 input 50 MHz.56d.Click Next.Figure 6-21 MegaWizard Plug-In Manager [page 3 of 14] Selections6.

Unselect all options on MegaWizard page 4. As you turn them off, pins disappear from the PLLblock’s graphical preview. See Figure 6-22 for an example.57Figure 6-22 MegaWizard Plug-In Manager [page 4 of 14] Selections7.Click Next four times to get to page 8.8.Set the Clock division factor to 10, as shown in Figure 6-23.58Figure 6-23 MegaWizard Plug-In Manager [page 8 of 14] Selections9.Click Next and then click Finish.10. The wizard displays a summary of the files it creates (see Figure 6-24). Select the pll.bsfoption and click Finish again.59Figure 6-24 Wizard-Created FilesThe Symbol window opens, showing the newly created PLL megafunction,a s shown in Figure6-25.60Figure 6-25 PLL Symbol11. Click OK and place the pll symbol onto the BDF to the left of the simple_counter symbol. Youcan drag and drop the symbols, if you need to rearrange them.

See Figure 6-26.Figure 6-26 Place the PLL Symbol12. Move the mouse so that the cursor (also called the selection tool) is over the pll symbol’s c0output pin. The orthogonal node tool (cross-hair) icon appears.13. Click and drag a bus line from the c0 output to the simple_counter clock input. This action tiesthe pll output to the simple_counter input (see Figure 6-27).61Figure 6-27 Draw a Bus Line connect pll c0 port to simple_counter CLOCK_5 portAdding an Input pin to the SchematicThe following steps describe how to add an input pin to the schematic.1.Right click in the blank area of the BDF and select Insert > Symbol.2.Under Libraries, select quartus/libraries > primitives > pin >input. See Figure 6-283.Click OKIf you need more room to place symbols, you can use the vertical and horizontal scroll bars at theedges of the BDF window to view more drawing space.Figure 6-28 Input pin symbol624.Place the new pin onto the BDF so that it is touching the input to the pll symbol.5.

Use the mouse to click and drag the new input pin to the left; notice that the ports remainconnected as shown in Figure 6-29.Figure 6-29 Connecting the PLL symbol and Input port6. Change the pin name by double-clicking pin_name and typing CLOCK_50 (see Figure 6-30).This name correlates to the oscillator clock that is connected to the FPGA.Adding an Output bus to the SchematicThe following steps describe how to add an output bus to the schematic.1.

Using the Orthogonal Bus tool, draw a bus line connected on one side to the simple_counteroutput port, and leave the other end unconnected at about 4 to 8 grid spaces to the right of thesimple_counter.63Figure 6-30 Change the input port name2.Right-click the new output bus line and select Properties.3.

Type counter [31..0] as the bus name (see Figure 6-31). The notation [X ..Y] is the Quartus IImethod for specifying the bus width in BDF schematics, where X is the most significant bit (MSB)and Y is the least significant bit (LSB).4.Click OK. Figure 6-32 shows the BDF.64Figure 6-31 Change the output BUS nameFigure 6-32 Circuit schematic (BDF)Adding a Multiplexer to the SchematicThis design uses a multiplexer to route the simple_counter output to the LED pins on the DE0-Nanodevelopment board. You will use the MegaWizard Plug-In Manager to add the multiplexer,lpm_mux.

The design multiplexes two portions of the counter bus to four LEDs on the DE0-Nanoboard. The following steps describe how to add a multiplexer to the schematic.651.Right click in the blank area of the BDF and select Insert > Symbol.2.Click Megawizard Plug-in Manager.3.Click Next.4.Select Installed Plug-Ins > Gates > LPM_MUX.5. Select the Cyclone IV E device family, Verilog HDL as the output file type, and name theoutput file counter_bus_mux.v, as shown in Figure 6-33.6.Click Next.Figure 6-33 Selecting lpm_mux7.Under “How many ‘data’ inputs do you want?” select 2 inputs (default).8. Under “How wide should the ‘data’ input and the ‘result’ output buses be?” select 4, as shownin Figure 6-34.66Figure 6-34 lpm_mux settings9.Click Next.10.

Click Next.11. Select the counter_bus_mux.bsf option.12.Click Finish. The Symbol window appears (see Figure 6-35 for an example).67Figure 6-35 lpm_mux Symbol13. Click OK14. Place the counter_bus_mux symbol below the existing symbols on the BDF, as shown inFigure 6-36.Figure 6-36 Place the lpm_mux symbol6815. Add input buses and output pins to the counter_bus_mux symbol as follows:a. Using the Orthogonal Bus tool, draw bus lines from the data1x[3..0] and data0x[3..0] inputports to about 8 to 12 grid spaces to the left of counter_bus_mux.b.

Draw a bus line from the result [3..0] output port to about 6 to 8 grid spaces to the right ofcounter_bus_mux.c.Right-click the bus line connected to data1x[3..0] and select Properties.d. Name the bus counter[26..23], which selects only those counter output bits to connect to thefour bits of the data1x input.Because the input busses to counter_bus_mux have the same names as the output bus fromsimple_counter, (counter[x .. y]) the Quartus II software knows to connect these busses.e.Click OK.f.Right-click the bus line connected to data0x[3..0] and select Properties.g.