Руководство пользователя для Altera DE0-Nano (Лабораторная работа 2), страница 4

Start the executable DE0_NANO_ControlPanel.exe on the host computer. The Control Paneluser interface shown in Figure 4-1 will appear.5. The DE0_NANO_ControlPanel.sof bit stream is loaded automatically as soon as theDE0_NANO_ControlPanel.exe is launched.6. In case the connection is disconnected, click on CONNECT where the .sof will be re-loadedonto the board.Note: the Control Panel will occupy the USB port until you choose to close the program ordisconnect it from the board by clicking the Disconnect button. While the Control Panel isconnected to the board, you will be unable to use Quartus II to download a configuration file intothe FPGA.268. The Control Panel is now ready for use; experience it by setting the ON/OFF status for someLEDs and observing the result on the DE0-Nano board.Figure 4-1 The DE0-Nano Control PanelThe concept of the DE0-Nano Control Panel is illustrated in Figure 4-2.

The “Control Circuit” thatperforms the control functions is implemented in the FPGA board. It communicates with theControl Panel window, which is active on the host computer, via the USB Blaster link. Thegraphical interface is used to issue commands to the control circuit. It handles all requests andperforms data transfers between the computer and the DE0-Nano board.Figure 4-2 The DE0-Nano Control Panel concept27The DE0-Nano Control Panel can be used to light up LEDs, change the buttons/switches status,read/write to SDRAM Memory, read ADC channels, and display the Accelerometer information.4.2 Controlling the LEDsA simple function of the Control Panel is to allow setting the values displayed on LEDs.

Choosingthe LED tab displays the window in Figure 4-3. Here, you can directly turn the LEDs on or offindividually or by clicking “Light All” or “Unlight All”.Figure 4-3 Controlling LEDs4.3 Switches and PushbuttonsChoosing the Switches tab displays the window in Figure 4-4. The function is designed to monitorthe status of slide switches and pushbuttons in real time and show the status in a graphical userinterface. It can be used to verify the functionality of the slide switches and pushbuttons.28Figure 4-4 Monitoring switches and buttonsThe ability to check the status of pushbutton and slider switches is not needed in typical designactivities.

However, it provides a simple mechanism for verifying if the buttons and switches arefunctioning correctly. Thus, it can be used for troubleshooting purposes.4.4 Memor y ControllerThe Control Panel can be used to write/read data to/from the SDRAM/EEPROM/EPCS on theDE0-Nano board. As an example, we will describe how the SDRAM may be accessed; the sameapproach is used to access the EEPROM and EPCS. Click on the Memory tab and select “SDRAM”to reach the window in Figure 4-5.29Figure 4-5 Accessing the SDRAMA 16-bit word can be written into the SDRAM by entering the address of the desired location,specifying the data to be written, and pressing the Write button.

Contents of the location can be readby pressing the Read button. Figure 4-5 depicts the result of writing the hexadecimal value 06CAinto offset address 200, followed by reading the same location.The Sequential Write function of the Control Panel is used to write the contents of a file into theSDRAM as follows:1.Specify the starting address in the Address box.2. Specify the number of bytes to be written in the Length box. If the entire file is to be loaded,then a checkmark may be placed in the File Length box instead of giving the number of bytes.3.To initiate the writing process, click on the Write a File to Memory button.4. When the Control Panel responds with the standard Windows dialog box asking for the sourcefile, specify the desired file in the usual manner.The Control Panel also supports loading files with a .hex extension.

Files with a .hex extension areASCII text files that specify memory values using ASCII characters to represent hexadecimalvalues. For example, a file containing the line0123456789ABCDEFdefines eight 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loadedconsecutively into the memory.The Sequential Read function is used to read the contents of the SDRAM and fill them into a file asfollows:301.Specify the starting address in the Address box.2.

Specify the number of bytes to be copied into the file in the Length box. If the entire contentsof the SDRAM are to be copied (which involves all 32 Mbytes), then place a checkmark in theEntire Memory box.3.Press Load Memory Content to a File button.4. When the Control Panel responds with the standard Windows dialog box asking for thedestination file, specify the desired file in the usual manner.Users can use the similar way to access the EEPROM and EPCS. Please note that users need toerase the EPCS before writing data to it.4.5 Digital AccelerometerThe Control Panel can be used to display the status of the Digital Accelerometer where it measuresthe output of its 3-axis (X, Y, Z).

The measurement range and resolution is set to default value ±2g(acceleration of gravity) and 10bit twos complement respectively. Figure 4-6 shows the currentdigital accelerometer status of the DE0-Nano when Accelerometer tab is clicked. The units that aredisplayed are the raw register values converted to decimal. The value in parentheses is thegravitational acceleration values (mg) calculated from the register values according the formula.Table 4-1 shows the rule.Table 4-1 acceleration values convert ruleRegister Value*FormulaResult (mg)00/511*2011/511*23.922/511*26.81717/511*266.4511511/511*2200031Figure 4-6 Digital Accelerometer status4.6 ADCFrom the Control Panel, users are able to view the eight-channel 12-bit analog-to-digital converterreading.

The values shown are the ADC register outputs from all of the eight separate channels. Thevoltage shown is the voltage reading from the separate pins on the extension header. Figure 4-7shows the ADC readings when the ADC tab is chosen.Figure 4-7 ADC Readings324.7 Overall Structure of the DE0-Nano Control PanelThe DE0-Nano Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV EFPGA with software running on the on-chip memory. The software part is implemented in C code;the hardware part is implemented in Verilog HDL code with SOPC builder. The source code is notavailable on the DE0-Nano System CD.To run the Control Panel, users should make the configuration according to Section 4.1.

Figure 4-8depicts the structure of the Control Panel. Each input/output device is controlled by the Nios IIProcessor instantiated in the FPGA chip. The communication with the PC is done via the USBBlaster link. The Nios II interprets the commands sent from the PC and performs the correspondingactions.Figure 4-8 The block diagram of the DE0-Nano Control Panel33Chapter 5DE0DE0-Nano System BuilderThis chapter describes how users can create a custom design project on the DE0-Nano board byusing DE0-Nano Tool – DE0-Nano System Builder.5.1 IntroductionThe DE0-Nano System Builder is a Windows based software utility, designed to assist users increating a Quartus II project for the DE0-Nano board within minutes. The generated Quartus IIproject files include:•••••Quartus II Project File (.qpf)Quartus II Setting File (.qsf)Top-Level Design File (.v)Synopsys Design Constraints file (.sdc)Pin Assignment Document (.htm)By providing the above files, DE0-Nano System Builder helps to prevents occurrence of situationsthat are prone to errors when users manually edit the top-level design file or place pin assignments.The common mistakes that users encounter are the following:1.Board damaged for wrong pin/bank voltage assignments.2.

Board malfunction caused by wrong device connections or missing pin counts for connectedends.3.Performance degeneration because of improper pin assignments.5.2 General Design FlowThis section will introduce the general design flow to build a project for the DE0-Nano board viathe DE0-Nano System Builder. The general design flow is illustrated in Figure 5-1.To create a new system using the DE0-Nano System Builder, begin by launching the DE0-NanoSystem Builder software. The software will then prompt you to specify the name of the project youwish to create, as well as the components on the DE0-Nano board you wish to you.

Once yourspecification is complete, you can generate the system.34The generated system is described using several files. In particular, there is the project file (.qpf),the top-level Verilog wrapper file (.v) that describes the I/O pins you will use in your design, andthe Quartus II settings file (.qsf) that specifies which pin on the FPGA each I/O in your designshould connect to. A Synopsys Design Constraints (.sdc) file with timing constraints and an HTMLfile with pin descriptions will be generated as well.To proceed with your design, open the Quartus II CAD software and open your newly-createdproject. You will now be able to implement the logic of your design by describing your design in ahardware description language, and connecting it to I/Os in the top-level wrapper file.

Once yourdesign is complete, compile the design using Quartus II, and then use the Quartus II Programmertool to configure the FPGA on the DE0-Nano board, using the JTAG programming mode.Figure 5-1The general design flow of building a design355.3 Using DE0-Nano System BuilderThis section provides the detailed procedures on how the to use the DE0-Nano System Builder.Install and launch the DE0-Nano System BuilderThe DE0-Nano System Builder is located in the directory: "Tools\DE0_NANO_SystemBuilder" onthe DE0-Nano System CD.