Микроконтроллер Motorola 68HC11, страница 10

SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.2. EPROG is present only in MC68HC711E20.3. ELAT in PPROG is present only on MC68HC711E9 and MC68S711E9.4. EEPROM mapping control bits EE[3:0] apply only to MC68HC811E2.Hardware priority is built into RAM and I/O mapping. Registers have priority over RAMand RAM has priority over ROM. When a lower priority resource is mapped at thesame location as a higher priority resource, a read/write of a location results in a read/write of the higher priority resource only. For example, if both the register block andthe RAM are mapped to the same location, only the register block will be accessed. IfRAM and ROM are located at the same position, RAM has priority.The fully static RAM can be used to store instructions, variables, and temporary data.The direct addressing mode can access RAM locations using a one-byte address operand, saving program memory space and execution time, depending on the application.RAM contents can be preserved during periods of processor inactivity by two methods, both of which reduce power consumption.In the software-based STOP mode, the clocks are stopped while VDD powers theMCU.

Because power supply current is directly related to operating frequency inCMOS integrated circuits, only a very small amount of leakage exists when the clocksare stopped.In the second method, the MODB/VSTBY pin can supply RAM power from a batterybackup or from a second power supply. Figure 4-5 shows a typical standby voltageMOTOROLA4-8OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATAcircuit for a standard 5 volt device. Adjustments to the circuit must be made for devicesthat operate at lower voltages.

Using the MODB/VSTBY pin may require external hardware, but can be justified when a significant amount of external circuitry is operatingfrom VDD. If VSTBY is used to maintain RAM contents, reset must be held low whenever VDD is below normal operating level.

Refer to SECTION 5 RESETS AND INTERRUPTS.VDDMAX690VDD4.7kVOUT4.8 VNiCdTO MODB/VSTBYOF M68HC11VBATT+4MODB/VSTBY CONNFigure 4-5 RAM Standby MODB/VSTBY ConnectionsThe bootloader program is contained in the internal bootstrap ROM. This ROM, whichappears as internal memory space at locations $BF00–$BFFF, is enabled only if theMCU is reset in special bootstrap mode.In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of resetand located at the top of the memory map if the ROMON bit in the CONFIG register isset. ROM or EPROM is enabled out of reset in single-chip and bootstrap modes, regardless of the state of ROMON.For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF andhas the same read cycle time as the internal ROM.

The 512 bytes of EEPROM cannotbe remapped to other locations.For the MC68HC811E2, EEPROM is located at $F800–$FFFF and can be remappedto any 4-Kbyte boundary. EEPROM mapping control bits (EE[3:0] in CONFIG) determine the location of the 2048 bytes of EEPROM and are present only on theMC68HC811E2. Refer to the description of the CONFIG register for MC68HC811E2.EEPROM can be programmed or erased by software and an on-chip charge pump,allowing EEPROM changes using the single 5 Vdc supply.4.2.1 Mode SelectionThe four mode variations are selected by the logic states of the MODA and MODB pinsduring reset. The MODA and MODB logic levels determine the logic state of SMODand the MDA control bits in the highest priority I-bit interrupt and miscellaneous (HPRIO) register.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-9After reset is released, the mode select pins no longer influence the MCU operatingmode.

In single-chip operating mode, the MODA pin is connected to a logic level zero.In expanded mode, MODA is normally connected to VDD through a pull-up resistor of4.7 kΩ. The MODA pin also functions as the load instruction register LIR pin when theMCU is not in reset. The open-drain active low LIR output pin drives low during the firstE cycle of each instruction. The MODB pin also functions as standby power input (VSTBY), which allows RAM contents to be maintained in absence of VDD.Refer to Table 4-2, which is a summary of mode pin operation, the mode control bits,and the four operating modes.Table 4-2 Hardware Mode Select SummaryInput Levelsat Reset4Control Bits in HPRIO(Latched at Reset)ModeMODBMODARBOOTSMODMDA1011Single Chip000Expanded00100Bootstrap11001Special Test011A normal mode is selected when MODB is logic one during reset.

One of three resetvectors is fetched from address $FFFA–$FFFF, and program execution begins fromthe address indicated by this vector. If MODB is logic zero during reset, the specialmode reset vector is fetched from addresses $BFFA–$BFFF and software has accessto special test features. Refer to SECTION 5 RESETS AND INTERRUPTS.HPRIO — Highest Priority I-Bit Interrupt and MiscellaneousRESET:$103CBit 7RBOOT1654SMOD1MDA1IRV(NE)13PSEL32PSEL21PSEL1Bit 0PSEL000100011010100010000111111110000Single ChipExpandedBootstrapTestNOTES:1. The reset values depend on the mode selected at power up.RBOOT — Read Bootstrap ROMValid only when SMOD is set (bootstrap or special test mode).

Can only be written inspecial modes.0 = Bootloader ROM disabled and not in map1 = Bootloader ROM enabled and in map at $BE00–$BFFFSMOD and MDA — Special Mode Select and Mode Select AThe initial value of SMOD is the inverse of the logic level present on the MODB pin atthe rising edge of reset. The initial value of MDA equals the logic level present on theMODA pin at the rising edge of reset. These two bits can be read at any time. Theycan be written anytime in special modes. MDA can only be written once in normalMOTOROLA4-10OPERATING MODES AND ON-CHIP MEMORYM68HC11 E SERIESTECHNICAL DATAmodes.

SMOD cannot be set once it has been cleared.InputsLatched at ResetModeMODBMODASMODMDA10Single Chip0011Expanded0100Bootstrap1001Special Test11IRV(NE) — Internal Read Visibility (/Not E)IRVNE can be written once in any mode. In expanded modes, IRVNE determineswhether IRV is on or off. In special test mode, IRVNE is reset to one. In all othermodes, IRVNE is reset to zero. For the MC68HC811E2, this bit is IRV and only controls the internal read visibility function.0 = No internal read visibility on external bus1 = Data from internal reads is driven out the external data bus.In single-chip modes this bit determines whether the E clock drives out from the chip.For the MC68HC811E2, this bit has no meaning or effect in single-chip and bootstrapmodes.0 = E is driven out from the chip.1 = E pin is driven low.

Refer to the following table.ModeIRVNE Outof ResetE Clock Outof ResetIRV Out ofResetIRVNEAffects OnlyIRVNE CanBe WrittenSingle Chip0OnOffEOnceExpanded0OnOffIRVOnceBootstrap0OnOffEOnceSpecial Test1OnOnIRVOncePSEL[3:0] — Priority Select Bits [3:0]Refer to SECTION 5 RESETS AND INTERRUPTS.4.2.2 System InitializationRegisters and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. The following table lists registers that can be written only once after reset or that must be written within the first 64cycles after reset.M68HC11 E SERIESTECHNICAL DATAOPERATING MODES AND ON-CHIP MEMORYMOTOROLA4-114Table 4-3 Write Access Limited RegistersOperatingModesRegisterAddressSMOD = 0SMOD = 14RegisterNameMust be Written inFirst 64 CyclesWriteAnytime$x024Timer Interrupt Mask 2 (TMSK2)Bits [1:0], once onlyBits [7:2]$x035Block Protect Register (BPROT)Clear bits, once onlySet bits only$x039System Configuration Options (OPTION)Bits [5:4], Bits [2:0], onceonlyBits [7:6], Bit 3$x03CHighest Priority I-Bit Interrupt and Miscellaneous (HPRIO)See HPRIOdescriptionSee HPRIOdescription$x03DRAM and I/O Map Register (INIT)Yes, once only—$x024Timer Interrupt Mask 2 (TMSK2)—All, set or clear$x035Block Protect Register (BPROT)—All, set or clear$x039System Configuration Options (OPTION)—All, set or clear$x03CHighest Priority I-Bit Interrupt andMiscellaneous (HPRIO)See HPRIOdescriptionSee HPRIOdescription$x03DRAM and I/O Map Register (INIT)—All, set or clear4.2.2.1 CONFIG RegisterThe CONFIG register consists of an EEPROM byte and static latches that control thestartup configuration of the MCU.