02-Creating-act- HDL Graphical Modules (1274893), страница 2

Просмтор этого файла доступен только зарегистрированным пользователям. Но у нас супер быстрая регистрация: достаточно только электронной почты!

Текст из файла (страница 2)

Watch as the VHDL code is generated from thestate diagram and then compiledActive-HDLautomaticallycreates corresponding VHDLcode for the state machine. Toopen the Control.vhd file in theHDL Editor window, doubleclick its name.Compile the top level blockdiagram top_counter.bdewww.aldec.com29Creating Fub Contents• The HDL Editor window••contains the code forthe state machine andhighlights the syntax toincrease readability.You can also generatethe structure for thecode to ease navigation.For more details on theHDL Editor, please referto the Bottom-Up DesignMethodology coursewww.aldec.com30Creating Graphical Process/Always• The Process/Always elements introduce another level of•abstraction in the Active-HDL projects. The GraphicalProcess/Always text blocks allow adding another form of thedescription in the designs that extensively employ blockdiagramsBy creating special textblocks representing VHDLprocessesorVerilogalways blocks, statementscan be placed directly on ablock diagram in the sameway as other typical HDLstatementswww.aldec.com31Creating Graphical Process/Always• They can be edited and connected with other objects on asheet and the list of signals/nets attached to the symbol isautomatically updated and displayed within the object framevisible in the block diagram window.

Graphical Process andGraphical Always can be edited directly in the Block DiagramEditor window or in the standalone HDL Editor windowwww.aldec.com32Objects View• The Objects View option allows you to view, sort and change••properties of all objects defined in a block diagram e.g. terminals,signals, generics, parameters, statements.The objects listed within this window can be put in the userdefined order by using the drag and drop technique.They can also be sorted in ascending or descending order or withthe default settings.www.aldec.com33Objects View• The final order applied by user is used while generating a code.• Additionally, the Objects View window allows for followingsignals/net and processes specified on block diagrams.www.aldec.com34Multiple Architectures support• The Block Diagram Editor allows for generating the VHDL code that•contains an architecture body only.This way different implementations (several architectures) for thesame entity can be created and used.www.aldec.com35Visible Port Direction• The purpose of this•feature is to make theport direction visible ona block diagram.It makes the analysis of ablock diagram easierespeciallywhenitcontains a large numberof complex symbols thathave different types ofports located on the leftand right side of thesymbol.www.aldec.com36Cross probing between BDE & HDE• The Show in Generated Code option is••available in context menu of selectedobject in the block diagram window.The Block Diagram Editor supportscross-probing between a diagram andthe generated code.It allows to link diagram objects (e.g.wires, buses, components, graphicalprocesses / always , other HDLstatements) with the HDL code and tosee the declaration of the selectedobject from a diagram directly in thecode.www.aldec.com37Bitmap support• The Block Diagram Editor•allows to place a picture(e.g.

company's logo) on ablock diagram from abitmap fileThe Block Diagram Editorsupports the followingpicture formats: Bitmap files (*.bmp) Windows Metafile files (*.wmf) Enhanced Metafile files (*.emf)www.aldec.com38Comments for diagram elements• The Block Diagram Editor allows••users to add comments for eachclass of block diagram elements.The terminals, wires, buses,symbols, and fubs can be describedby an additional text field selectedfromtheobjectpropertiesComment tab.The comments appearing ondiagrams as well as in the generatedHDL code are very helpful whiledocumenting or during the analysisof complex designswww.aldec.com39I/O port conversion functions• Block Diagram will automatically insert conversion function for••those pins of a symbol that have a type different than the defaulttype of signals used on a block diagramIt is possible to manually specify the conversion function for aterminal and connected signal.This option allows using user-defined types on block diagrams.www.aldec.com40Add Stubs features• The Add Stubs option automatically adds wires and/or buses to•unconnected ports of the symbol and assigns them names properfor individual ports of the symbol.This significantly speeds up the process of creating interconnectusing named association.www.aldec.com41State Diagram Editor features••••••••••••••Multiple architectures supportCode Generation SettingsAutomatic Testbench generation for state diagramsHDL code editingAsynchronous machinesMultiple reset supportTransition Auto PriorityJunctionConvert to Hierarchical StateState register portSynthesis AttributesExport to previous ASF formatReport file generationDelay state for asynchronous machineswww.aldec.com42Multiple State Machines• The Active-HDL State Diagram Editor allows to describe thebehavior of a design unit using multiple concurrent state diagramsin one document.• The space on the diagram hasto be partitioned and the NewMachine menu option willcreate a frame for the newstate machine.www.aldec.com43Multiple Architectures support-FSM• The•State DiagramEditorallowstogenerate the VHDLcode that contains anarchitecture body only.This way you can createandusedifferentimplementations(several architectures)for the same entity.www.aldec.com44Code Generation Settings-FSMCode Generation Settings dialog (Image on next page):• To generate a code from a state diagram, you can set several HDL styles.• You can decide whether to use the if or case statements in the state••••register description.Additionally, you can choose the final form of your state machine logic,that is, whether it will be described by using one, two, or three processes.Users can control the header and comments insertion in the generatedcode.The State Diagram Editor allows you to choose the clock specification inthe generated code.The State Diagram Editor allows designers to use blocking or nonblocking assignments in the generated code.www.aldec.com45Code Generation Settings-FSMwww.aldec.com46Automatic Testbench generation for FSM• The State Diagram Editor••allows users to automaticallypreparetestbenchesforprojects of state machines.Users have up to threestrategies of testing that canbe set individually for specificneeds in your projects.The purpose of this feature isto speed up the verificationprocess of design unitsdescribed by means of thestate diagram.www.aldec.com47HDL code editing• The Edit Using HDE option has•been added to the StateDiagram Editor's Preferences.It allows users to automaticallyopen the standalone HDLEditor window for editing stateactions.www.aldec.com48Asynchronous machines• The State Diagram Editor•supports the creation ofasynchronous state machines.If you create this type of statemachine,youcansetappropriate options in theMachine Properties window.www.aldec.com49Multiple Reset support• The State Diagram Editor allows to specify several reset signals instate machine projects.www.aldec.com50Transition Auto Priority• The Transition Auto Priority option has been enabled in the StateMachine Editor.

If several transitions come out of one state, theirpriorities will be assigned automatically. It allows avoiding theambiguity in the machine's behavior in case two or moreconditions are met at the same time.www.aldec.com51Junction• The••Junction is anadditionalgraphicalobject that simplifies thecreation and analysis ofstate diagrams.Junction is a "connector"that enables a set oftransitions to be replacedby another reduced set ofstate-to-state transitions.The less transitions on astate diagram, the easierits evaluation is.www.aldec.com52Convert to Hierarchical State• Once a part of the state diagram has been selected, it can beconverted to a Hierarchical State. If you work on very complexstate machine projects, you can use Convert to Hierarchical Stateoption to decompose your machine and make the resultingdiagram easier to document and analyze for you and otherdesigners.www.aldec.com53Covert to Hierarchical Statewww.aldec.com54Delay State• Delay state does not determinethe machine's outputs but itdefines a period of time that mustelapse before a transition fromone state to another occurs onthe active clock edge.

Характеристики

Список файлов книги